forked from OSchip/llvm-project
[SelectionDAG] Implement PromoteIntRes_INSERT_SUBVECTOR
Inserting into a smaller-than-legal scalable vector would result in an internal compiler error. For example, inserting a <vscale x 4 x i8> into a <vscale x 8 x i8> (both illegal vector types for SVE) would cause a crash. This crash was happening because there was no code to promote (legalise) the result of an INSERT_SUBVECTOR node. This patch implements PromoteIntRes_INSERT_SUBVECTOR, which legalises the ISD node. This is currently done by going through memory. This is necessary because of the requirement that the SubVec parameter of the INSERT_SUBVECTOR node must be smaller than the Vec parameter, which means that INSERT_SUBVECTOR cannot always have a legal result/operand types. Co-Authored-by: Joe Ellis <joe.ellis@arm.com> Differential Revision: https://reviews.llvm.org/D102766
This commit is contained in:
Bradley Smith
parent
661577e698
commit
2668727929
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@ -97,6 +97,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
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case ISD::EXTRACT_SUBVECTOR:
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Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
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case ISD::INSERT_SUBVECTOR:
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Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
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case ISD::VECTOR_REVERSE:
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Res = PromoteIntRes_VECTOR_REVERSE(N); break;
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case ISD::VECTOR_SHUFFLE:
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@ -4729,6 +4731,50 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
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return DAG.getBuildVector(NOutVT, dl, Ops);
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_SUBVECTOR(SDNode *N) {
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EVT OutVT = N->getValueType(0);
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EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
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assert(NOutVT.isVector() && "This type must be promoted to a vector type");
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SDLoc dl(N);
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SDValue Vec = N->getOperand(0);
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SDValue SubVec = N->getOperand(1);
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SDValue Idx = N->getOperand(2);
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auto *ConstantIdx = cast<ConstantSDNode>(Idx);
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unsigned IdxN = ConstantIdx->getZExtValue();
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EVT VecVT = Vec.getValueType();
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EVT SubVecVT = SubVec.getValueType();
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// To insert SubVec into Vec, store the wider vector to memory, overwrite the
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// appropriate bits with the narrower vector, and reload.
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Align SmallestAlign = DAG.getReducedAlign(SubVecVT, /*UseABI=*/false);
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SDValue StackPtr =
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DAG.CreateStackTemporary(VecVT.getStoreSize(), SmallestAlign);
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auto StackPtrVT = StackPtr->getValueType(0);
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auto &MF = DAG.getMachineFunction();
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auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
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auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
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SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
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SmallestAlign);
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SDValue ScaledIdx = Idx;
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if (SubVecVT.isScalableVector() && IdxN != 0) {
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APInt IdxAPInt = cast<ConstantSDNode>(Idx)->getAPIntValue();
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ScaledIdx = DAG.getVScale(dl, StackPtrVT,
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IdxAPInt.sextOrSelf(StackPtrVT.getSizeInBits()));
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}
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SDValue SubVecPtr =
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TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, ScaledIdx);
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Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, PtrInfo, SmallestAlign);
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return DAG.getExtLoad(ISD::LoadExtType::EXTLOAD, dl, NOutVT, Store, StackPtr,
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PtrInfo, OutVT, SmallestAlign);
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
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SDLoc dl(N);
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@ -298,6 +298,7 @@ private:
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SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
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SDValue PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N, unsigned ResNo);
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SDValue PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N);
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SDValue PromoteIntRes_INSERT_SUBVECTOR(SDNode *N);
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SDValue PromoteIntRes_VECTOR_REVERSE(SDNode *N);
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SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N);
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SDValue PromoteIntRes_VECTOR_SPLICE(SDNode *N);
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@ -7837,11 +7837,13 @@ SDValue TargetLowering::getVectorSubVecPointer(SelectionDAG &DAG,
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assert(EltSize * 8 == EltVT.getFixedSizeInBits() &&
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"Converting bits to bytes lost precision");
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assert(SubVecVT.isFixedLengthVector() &&
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SubVecVT.getVectorElementType() == EltVT &&
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"Sub-vector must be a fixed vector with matching element type");
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Index = clampDynamicVectorIndex(DAG, Index, VecVT, dl,
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SubVecVT.getVectorNumElements());
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// Scalable vectors don't need clamping as these are checked at compile time
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if (SubVecVT.isFixedLengthVector()) {
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assert(SubVecVT.getVectorElementType() == EltVT &&
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"Sub-vector must be a fixed vector with matching element type");
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Index = clampDynamicVectorIndex(DAG, Index, VecVT, dl,
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SubVecVT.getVectorNumElements());
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}
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EVT IdxVT = Index.getValueType();
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@ -17100,6 +17100,10 @@ void AArch64TargetLowering::ReplaceNodeResults(
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case ISD::EXTRACT_SUBVECTOR:
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ReplaceExtractSubVectorResults(N, Results, DAG);
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return;
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case ISD::INSERT_SUBVECTOR:
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// Custom lowering has been requested for INSERT_SUBVECTOR -- but delegate
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// to common code for result type legalisation
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return;
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case ISD::INTRINSIC_WO_CHAIN: {
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EVT VT = N->getValueType(0);
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assert((VT == MVT::i8 || VT == MVT::i16) &&
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@ -0,0 +1,276 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; SCALABLE INSERTED INTO SCALABLE TESTS
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define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_zero_i8(<vscale x 8 x i8>* %a, <vscale x 4 x i8>* %b) #0 {
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; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ld1b { z1.s }, p1/z, [x1]
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; CHECK-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: st1b { z1.s }, p1, [sp, #2, mul vl]
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
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%subvec = load <vscale x 4 x i8>, <vscale x 4 x i8>* %b
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%ins = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> %vec, <vscale x 4 x i8> %subvec, i64 0)
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ret <vscale x 8 x i8> %ins
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}
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define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_nonzero_i8(<vscale x 8 x i8>* %a, <vscale x 4 x i8>* %b) #0 {
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; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ld1b { z1.s }, p1/z, [x1]
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; CHECK-NEXT: addpl x8, sp, #4
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; CHECK-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: st1b { z1.s }, p1, [x8, #1, mul vl]
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
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%subvec = load <vscale x 4 x i8>, <vscale x 4 x i8>* %b
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%ins = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> %vec, <vscale x 4 x i8> %subvec, i64 4)
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ret <vscale x 8 x i8> %ins
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}
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define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_zero_i16(<vscale x 4 x i16>* %a, <vscale x 2 x i16>* %b) #0 {
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; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z1.d }, p1/z, [x1]
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; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: st1h { z1.d }, p1, [sp, #2, mul vl]
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
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%subvec = load <vscale x 2 x i16>, <vscale x 2 x i16>* %b
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%ins = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 0)
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ret <vscale x 4 x i16> %ins
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}
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define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_nonzero_i16(<vscale x 4 x i16>* %a, <vscale x 2 x i16>* %b) #0 {
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; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z1.d }, p1/z, [x1]
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; CHECK-NEXT: addpl x8, sp, #4
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; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: st1h { z1.d }, p1, [x8, #1, mul vl]
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
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%subvec = load <vscale x 2 x i16>, <vscale x 2 x i16>* %b
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%ins = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 2)
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ret <vscale x 4 x i16> %ins
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}
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; FIXED INSERTED INTO SCALABLE TESTS
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define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_zero_i8(<vscale x 8 x i8>* %a, <8 x i8>* %b) #0 {
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; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: addpl x8, sp, #4
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; CHECK-NEXT: str d1, [x8]
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
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%subvec = load <8 x i8>, <8 x i8>* %b
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%ins = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8> %vec, <8 x i8> %subvec, i64 0)
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ret <vscale x 8 x i8> %ins
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}
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define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_nonzero_i8(<vscale x 8 x i8>* %a, <8 x i8>* %b) #0 {
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; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: cnth x9
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; CHECK-NEXT: addpl x10, sp, #4
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: sub x9, x9, #8 // =8
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; CHECK-NEXT: mov w8, #8
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; CHECK-NEXT: cmp x9, #8 // =8
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; CHECK-NEXT: csel x8, x9, x8, lo
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; CHECK-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: str d1, [x10, x8]
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
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%subvec = load <8 x i8>, <8 x i8>* %b
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%ins = call <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8> %vec, <8 x i8> %subvec, i64 8)
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ret <vscale x 8 x i8> %ins
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}
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define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_zero_i16(<vscale x 4 x i16>* %a, <4 x i16>* %b) #0 {
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; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: addpl x8, sp, #4
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; CHECK-NEXT: str d1, [x8]
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
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%subvec = load <4 x i16>, <4 x i16>* %b
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%ins = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16> %vec, <4 x i16> %subvec, i64 0)
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ret <vscale x 4 x i16> %ins
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}
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define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_nonzero_i16(<vscale x 4 x i16>* %a, <4 x i16>* %b) #0 {
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; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: cntw x9
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: sub x9, x9, #4 // =4
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; CHECK-NEXT: mov w8, #4
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; CHECK-NEXT: cmp x9, #4 // =4
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; CHECK-NEXT: csel x8, x9, x8, lo
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; CHECK-NEXT: addpl x9, sp, #4
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; CHECK-NEXT: lsl x8, x8, #1
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; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: str d1, [x9, x8]
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
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%subvec = load <4 x i16>, <4 x i16>* %b
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%ins = call <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16> %vec, <4 x i16> %subvec, i64 4)
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ret <vscale x 4 x i16> %ins
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}
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define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_zero_i32(<vscale x 2 x i32>* %a, <2 x i32>* %b) #0 {
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; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: addpl x8, sp, #4
|
||||
; CHECK-NEXT: str d1, [x8]
|
||||
; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a
|
||||
%subvec = load <2 x i32>, <2 x i32>* %b
|
||||
%ins = call <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32> %vec, <2 x i32> %subvec, i64 0)
|
||||
ret <vscale x 2 x i32> %ins
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_i32(<vscale x 2 x i32>* %a, <2 x i32>* %b) #0 {
|
||||
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: ptrue p0.d
|
||||
; CHECK-NEXT: cntd x9
|
||||
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
|
||||
; CHECK-NEXT: ldr d1, [x1]
|
||||
; CHECK-NEXT: sub x9, x9, #2 // =2
|
||||
; CHECK-NEXT: mov w8, #2
|
||||
; CHECK-NEXT: cmp x9, #2 // =2
|
||||
; CHECK-NEXT: csel x8, x9, x8, lo
|
||||
; CHECK-NEXT: addpl x9, sp, #4
|
||||
; CHECK-NEXT: lsl x8, x8, #2
|
||||
; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
|
||||
; CHECK-NEXT: str d1, [x9, x8]
|
||||
; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a
|
||||
%subvec = load <2 x i32>, <2 x i32>* %b
|
||||
%ins = call <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32> %vec, <2 x i32> %subvec, i64 2)
|
||||
ret <vscale x 2 x i32> %ins
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_large_i32(<vscale x 2 x i32>* %a, <8 x i32>* %b) #0 {
|
||||
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_large_i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: cntd x8
|
||||
; CHECK-NEXT: ptrue p0.d
|
||||
; CHECK-NEXT: subs x8, x8, #8 // =8
|
||||
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
|
||||
; CHECK-NEXT: ldp q1, q2, [x1]
|
||||
; CHECK-NEXT: csel x8, xzr, x8, lo
|
||||
; CHECK-NEXT: mov w9, #8
|
||||
; CHECK-NEXT: cmp x8, #8 // =8
|
||||
; CHECK-NEXT: csel x8, x8, x9, lo
|
||||
; CHECK-NEXT: mov x9, sp
|
||||
; CHECK-NEXT: add x8, x9, x8, lsl #2
|
||||
; CHECK-NEXT: st1w { z0.d }, p0, [sp]
|
||||
; CHECK-NEXT: stp q1, q2, [x8]
|
||||
; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a
|
||||
%subvec = load <8 x i32>, <8 x i32>* %b
|
||||
%ins = call <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> %vec, <8 x i32> %subvec, i64 8)
|
||||
ret <vscale x 2 x i32> %ins
|
||||
}
|
||||
|
||||
declare <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8>, <vscale x 4 x i8>, i64)
|
||||
declare <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16>, <vscale x 2 x i16>, i64)
|
||||
|
||||
declare <vscale x 8 x i8> @llvm.experimental.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8>, <8 x i8>, i64)
|
||||
declare <vscale x 4 x i16> @llvm.experimental.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16>, <4 x i16>, i64)
|
||||
declare <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32>, <2 x i32>, i64)
|
||||
|
||||
declare <vscale x 2 x i32> @llvm.experimental.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64)
|
||||
|
||||
attributes #0 = { nounwind "target-features"="+sve" }
|
||||
Loading…
Reference in New Issue