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Make the addressing modes smarter 

llvm-svn: 24795
This commit is contained in:
Chris Lattner 2005-12-17 21:25:27 +00:00
parent 19ff62dc67
commit 2616a0b56f
2 changed files with 21 additions and 10 deletions
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27
llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@ -235,18 +235,33 @@ void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
ScheduleAndEmitDAG(DAG);
}
bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand N, SDOperand &R1,
bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
SDOperand &R2) {
// FIXME: This should obviously be smarter.
R1 = Select(N);
if (Addr.getOpcode() == ISD::ADD) {
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).Val))
return false; // Let the reg+imm pattern catch this!
R1 = Addr.getOperand(0);
R2 = Addr.getOperand(1);
return true;
}
R1 = Select(Addr);
R2 = CurDAG->getRegister(V8::G0, MVT::i32);
return true;
}
bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand N, SDOperand &Base,
bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
SDOperand &Offset) {
// FIXME: This should obviously be smarter.
Base = Select(N);
if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
if (Predicate_simm13(CN)) {
Base = Addr.getOperand(0);
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
return true;
}
}
Base = Select(Addr);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}

4
llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -90,10 +90,6 @@ def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
// Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL:
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
def RET : F3_2<2, 0b111000,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"ret $b, $c, $dst", []>;
let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
def RETL: F3_2<2, 0b111000, (ops),
"retl", [(ret)]>;