forked from OSchip/llvm-project
- Changes how function livein's are handled, they now have a start index of 0.
- When coalescing a copy MI, if its destination is "dead", propagate the property to the source MI's destination if there are no intervening uses. - Detect dead function live-in's and remove them. llvm-svn: 34383
This commit is contained in:
parent
a3d3599210
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2605082f0e
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@ -118,6 +118,11 @@ namespace llvm {
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return I->second;
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}
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bool hasInterval(unsigned reg) const {
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Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
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return I != r2iMap_.end();
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}
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/// getMBBStartIdx - Return the base index of the first instruction in the
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/// specified MachineBasicBlock.
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unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
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@ -189,6 +194,7 @@ namespace llvm {
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/// copies that cannot yet be coallesced into the "TryAgain" list.
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void CopyCoallesceInMBB(MachineBasicBlock *MBB,
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std::vector<CopyRec> &TryAgain);
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns true
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/// if the copy was successfully coallesced away, or if it is never possible
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@ -233,6 +239,9 @@ namespace llvm {
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LiveInterval &interval,
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unsigned SrcReg);
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/// handleLiveInRegister - Create interval for a livein register.
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void handleLiveInRegister(MachineBasicBlock* mbb, LiveInterval &interval);
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/// Return true if the two specified registers belong to different
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/// register classes. The registers may be either phys or virt regs.
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bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
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@ -241,11 +250,16 @@ namespace llvm {
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bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
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MachineInstr *CopyMI);
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bool overlapsAliases(const LiveInterval *lhs,
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const LiveInterval *rhs) const;
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/// hasRegisterUse - Returns true if there is any use of the specific
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/// reg between indexes Start and End.
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bool hasRegisterUse(unsigned Reg, unsigned Start, unsigned End);
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static LiveInterval createInterval(unsigned Reg);
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void removeInterval(unsigned Reg) {
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r2iMap_.erase(Reg);
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}
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LiveInterval &getOrCreateInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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if (I == r2iMap_.end())
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@ -98,28 +98,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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// Set the MBB2IdxMap entry for this MBB.
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MBB2IdxMap[MBB->getNumber()] = MIIndex;
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// If this BB has any live ins, insert a dummy instruction at the
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// beginning of the function that we will pretend "defines" the values. This
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// is to make the interval analysis simpler by providing a number.
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if (MBB->livein_begin() != MBB->livein_end()) {
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unsigned FirstLiveIn = *MBB->livein_begin();
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// Find a reg class that contains this live in.
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const TargetRegisterClass *RC = 0;
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for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
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RCE = mri_->regclass_end(); RCI != RCE; ++RCI)
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if ((*RCI)->contains(FirstLiveIn)) {
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RC = *RCI;
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break;
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}
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MachineInstr *OldFirstMI = MBB->begin();
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mri_->copyRegToReg(*MBB, MBB->begin(),
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FirstLiveIn, FirstLiveIn, RC);
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assert(OldFirstMI != MBB->begin() &&
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"copyRetToReg didn't insert anything!");
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}
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
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@ -161,7 +139,16 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
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(RegRep = rep(srcReg)) == rep(dstReg)) {
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// remove from def list
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getOrCreateInterval(RegRep);
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LiveInterval &RegInt = getOrCreateInterval(RegRep);
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MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
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// If def of this move instruction is dead, remove its live range from
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// the dstination register's live interval.
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if (MO->isDead()) {
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unsigned MoveIdx = getDefIndex(getInstructionIndex(mii));
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RegInt.removeRange(*RegInt.FindLiveRangeContaining(MoveIdx));
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if (RegInt.empty())
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removeInterval(RegRep);
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}
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RemoveMachineInstrFromMaps(mii);
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mii = mbbi->erase(mii);
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++numPeep;
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@ -185,7 +172,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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}
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}
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for (iterator I = begin(), E = end(); I != E; ++I) {
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LiveInterval &LI = I->second;
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if (MRegisterInfo::isVirtualRegister(LI.reg)) {
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@ -670,6 +656,43 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
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}
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}
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void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
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LiveInterval &interval) {
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DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
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// Look for kills, if it reaches a def before it's killed, then it shouldn't
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// be considered a livein.
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MachineBasicBlock::iterator mi = MBB->begin();
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unsigned baseIndex = 0;
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unsigned start = 0;
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unsigned end = start;
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while (mi != MBB->end()) {
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if (lv_->KillsRegister(mi, interval.reg)) {
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DOUT << " killed";
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end = getUseIndex(baseIndex) + 1;
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goto exit;
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} else if (lv_->ModifiesRegister(mi, interval.reg)) {
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// Another instruction redefines the register before it is ever read.
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// Then the register is essentially dead at the instruction that defines
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// it. Hence its interval is:
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// [defSlot(def), defSlot(def)+1)
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DOUT << " dead";
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end = getDefIndex(start) + 1;
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goto exit;
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}
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baseIndex += InstrSlots::NUM;
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++mi;
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}
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exit:
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assert(start < end && "did not find end of interval?");
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LiveRange LR(start, end, interval.getNextValue(~0U, 0));
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interval.addRange(LR);
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DOUT << " +" << LR << '\n';
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}
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/// computeIntervals - computes the live intervals for virtual
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/// registers. for some ordering of the machine instructions [1,N] a
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/// live interval is an interval [i, j) where 1 <= i <= j < N for
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@ -688,17 +711,13 @@ void LiveIntervals::computeIntervals() {
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MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
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if (MBB->livein_begin() != MBB->livein_end()) {
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// Process live-ins to this BB first.
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for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
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// Create intervals for live-ins to this BB first.
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for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
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LE = MBB->livein_end(); LI != LE; ++LI) {
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handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
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getOrCreateInterval(*LI), 0);
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handleLiveInRegister(MBB, getOrCreateInterval(*LI));
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for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS)
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handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
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getOrCreateInterval(*AS), 0);
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handleLiveInRegister(MBB, getOrCreateInterval(*AS));
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}
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++MI;
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MIIndex += InstrSlots::NUM;
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}
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for (; MI != miEnd; ++MI) {
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@ -815,7 +834,6 @@ bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
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return true;
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}
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns true
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/// if the copy was successfully coallesced away, or if it is never possible
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@ -827,52 +845,91 @@ bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
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DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
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// Get representative registers.
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SrcReg = rep(SrcReg);
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DstReg = rep(DstReg);
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unsigned repSrcReg = rep(SrcReg);
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unsigned repDstReg = rep(DstReg);
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// If they are already joined we continue.
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if (SrcReg == DstReg) {
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if (repSrcReg == repDstReg) {
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DOUT << "\tCopy already coallesced.\n";
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return true; // Not coallescable.
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}
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// If they are both physical registers, we cannot join them.
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if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
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MRegisterInfo::isPhysicalRegister(DstReg)) {
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if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
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MRegisterInfo::isPhysicalRegister(repDstReg)) {
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DOUT << "\tCan not coallesce physregs.\n";
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return true; // Not coallescable.
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}
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// We only join virtual registers with allocatable physical registers.
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if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
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if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
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!allocatableRegs_[repSrcReg]) {
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DOUT << "\tSrc reg is unallocatable physreg.\n";
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return true; // Not coallescable.
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}
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if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
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if (MRegisterInfo::isPhysicalRegister(repDstReg) &&
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!allocatableRegs_[repDstReg]) {
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DOUT << "\tDst reg is unallocatable physreg.\n";
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return true; // Not coallescable.
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}
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// If they are not of the same register class, we cannot join them.
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if (differingRegisterClasses(SrcReg, DstReg)) {
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if (differingRegisterClasses(repSrcReg, repDstReg)) {
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DOUT << "\tSrc/Dest are different register classes.\n";
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return true; // Not coallescable.
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}
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LiveInterval &SrcInt = getInterval(SrcReg);
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LiveInterval &DestInt = getInterval(DstReg);
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assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
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LiveInterval &SrcInt = getInterval(repSrcReg);
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LiveInterval &DestInt = getInterval(repDstReg);
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assert(SrcInt.reg == repSrcReg && DestInt.reg == repDstReg &&
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"Register mapping is horribly broken!");
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DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
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DOUT << " and "; DestInt.print(DOUT, mri_);
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DOUT << ": ";
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// Check if it is necessary to propagate "isDead" property before intervals
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// are joined.
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MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
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bool isDead = mopd->isDead();
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unsigned SrcStart = 0;
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unsigned SrcEnd = 0;
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if (isDead) {
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unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
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LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx-1);
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SrcStart = SrcLR->start;
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SrcEnd = SrcLR->end;
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if (hasRegisterUse(repSrcReg, SrcStart, SrcEnd))
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isDead = false;
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}
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// Okay, attempt to join these two intervals. On failure, this returns false.
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// Otherwise, if one of the intervals being joined is a physreg, this method
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// always canonicalizes DestInt to be it. The output "SrcInt" will not have
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// been modified, so we can use this information below to update aliases.
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if (!JoinIntervals(DestInt, SrcInt)) {
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if (JoinIntervals(DestInt, SrcInt)) {
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if (isDead) {
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// Result of the copy is dead. Propagate this property.
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if (SrcStart == 0) {
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// Live-in to the function but dead. Remove it from MBB live-in set.
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// JoinIntervals may end up swapping the two intervals.
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LiveInterval &LiveInInt = (repSrcReg == DestInt.reg) ? DestInt:SrcInt;
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LiveInInt.removeRange(SrcStart, SrcEnd);
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MachineBasicBlock *MBB = CopyMI->getParent();
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MBB->removeLiveIn(SrcReg);
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} else {
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MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
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if (SrcMI) {
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// FIXME: SrcMI == NULL means the register is livein to a non-entry
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// MBB. Remove the range from its live interval?
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MachineOperand *mops = SrcMI->findRegisterDefOperand(SrcReg);
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if (mops)
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// FIXME: mops == NULL means SrcMI defines a subregister?
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mops->setIsDead();
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}
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}
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}
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} else {
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// Coallescing failed.
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// If we can eliminate the copy without merging the live ranges, do so now.
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@ -884,17 +941,17 @@ bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
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return false;
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}
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bool Swapped = SrcReg == DestInt.reg;
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bool Swapped = repSrcReg == DestInt.reg;
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if (Swapped)
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std::swap(SrcReg, DstReg);
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assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
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std::swap(repSrcReg, repDstReg);
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assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
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"LiveInterval::join didn't work right!");
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// If we're about to merge live ranges into a physical register live range,
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// we have to update any aliased register's live ranges to indicate that they
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// have clobbered values for this range.
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if (MRegisterInfo::isPhysicalRegister(DstReg)) {
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for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS)
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if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
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for (const unsigned *AS = mri_->getAliasSet(repDstReg); *AS; ++AS)
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getInterval(*AS).MergeInClobberRanges(SrcInt);
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}
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@ -904,8 +961,8 @@ bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
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// If the intervals were swapped by Join, swap them back so that the register
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// mapping (in the r2i map) is correct.
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if (Swapped) SrcInt.swap(DestInt);
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r2iMap_.erase(SrcReg);
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r2rMap_[SrcReg] = DstReg;
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removeInterval(repSrcReg);
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r2rMap_[repSrcReg] = repDstReg;
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// Finally, delete the copy instruction.
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RemoveMachineInstrFromMaps(CopyMI);
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@ -1389,6 +1446,29 @@ bool LiveIntervals::differingRegisterClasses(unsigned RegA,
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return !RegClass->contains(RegB);
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}
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/// hasRegisterUse - Returns true if there is any use of the specific
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/// reg between indexes Start and End.
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bool
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LiveIntervals::hasRegisterUse(unsigned Reg, unsigned Start, unsigned End) {
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for (unsigned Index = Start+InstrSlots::NUM; Index != End;
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Index += InstrSlots::NUM) {
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// Skip deleted instructions
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while (Index != End && !getInstructionFromIndex(Index))
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Index += InstrSlots::NUM;
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if (Index >= End) break;
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MachineInstr *MI = getInstructionFromIndex(Index);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isUse() && MO.getReg() &&
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mri_->regsOverlap(rep(MO.getReg()), Reg))
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return true;
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}
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}
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return false;
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}
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LiveInterval LiveIntervals::createInterval(unsigned reg) {
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float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
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HUGE_VALF : 0.0F;
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