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Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work 

with 32 or 64-bit operands/results.

llvm-svn: 48026
This commit is contained in:
Chris Lattner 2008-03-07 20:13:51 +00:00
parent 910e9de131
commit 25ff7e217d
1 changed files with 3 additions and 6 deletions
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9
llvm/lib/Target/PowerPC/PPCInstrInfo.td
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@ -20,9 +20,6 @@ include "PPCInstrFormats.td"
def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
SDTCisVT<0, f64>, SDTCisPtrTy<1>
]>;
def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
]>;
def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
SDTCisVT<1, i32> ]>;
@ -84,9 +81,9 @@ def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
// amounts. These nodes are generated by the multi-precision shift code.
def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntBinOp>;
def PPCsra : SDNode<"PPCISD::SRA" , SDTIntBinOp>;
def PPCshl : SDNode<"PPCISD::SHL" , SDTIntBinOp>;
def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,