forked from OSchip/llvm-project
Added the initial version of the TableGen description for the Sparc backend.
llvm-svn: 6021
This commit is contained in:
Misha Brukman
parent
adf5519a1c
commit
25e907dae4
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//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-Independent interface
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//===----------------------------------------------------------------------===//
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class Register {
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string Namespace = "";
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int Size;
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}
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class Instruction {
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string Name; // The opcode string for this instruction
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string Namespace = "";
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list<Register> Uses = []; // Default to using no non-operand registers
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list<Register> Defs = []; // Default to modifying no non-operand registers
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// These bits capture information about the high-level semantics of the
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// instruction.
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bit isReturn = 0; // Is this instruction a return instruction?
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bit isBranch = 0; // Is this instruction a branch instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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}
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//===----------------------------------------------------------------------===//
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// Declarations that describe the Sparc register file
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//===----------------------------------------------------------------------===//
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class V9Reg : Register { set Namespace = "SparcV9"; }
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// Ri - One of the 32 64 bit integer registers
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class Ri<bits<5> num> : V9Reg { set Size = 64; field bits<5> Num = num; }
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def G0 : Ri<0>; def G1 : Ri<1>; def G2 : Ri<2>; def G3 : Ri<3>;
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// ...
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//===----------------------------------------------------------------------===//
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// This is temporary testing stuff.....
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//===----------------------------------------------------------------------===//
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class InstV9 : Instruction { // Sparc instruction baseline
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field bits<32> Inst;
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set Namespace = "SparcV9";
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bits<2> op;
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set Inst{31-30} = op; // Top two bits are the 'op' field
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// Bit attributes specific to Sparc instructions
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bit isPasi = 0; // Does this instruction affect an alternate addr space?
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bit isDeprecated = 0; // Is this instruction deprecated?
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bit isPrivileged = 0; // Is this a privileged instruction?
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}
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//===----------------------------------------------------------------------===//
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// Format #2 classes
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//
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class F2 : InstV9 { // Format 2 instructions
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bits<3> op2;
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set op = 0; // Op = 0
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set Inst{24-22} = op2;
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}
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class F2_br : F2 { // Format 2 Branch instruction
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bit annul; // All branches have an annul bit
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set Inst{29} = annul;
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set isBranch = 1; // All instances are branch instructions
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}
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class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
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bits<22> disp;
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set Name = name;
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set Inst{28-25} = cond;
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set Inst{21-0} = disp;
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}
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class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
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bits<2> cc;
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bits<19> disp;
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bit predict;
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set Name = name;
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set Inst{28-25} = cond;
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set Inst{21-20} = cc;
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set Inst{19} = predict;
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set Inst{18-0} = disp;
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}
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class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
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// Variables exposed by the instruction...
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bit predict;
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bits<5> rs1;
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bits<16> disp;
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set Name = name;
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set Inst{28} = 0;
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set Inst{27-25} = rcond;
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// Inst{24-22} = op2 field
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set Inst{21-20} = disp{15-14};
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set Inst{19} = predict;
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set Inst{18-14} = rs1;
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set Inst{13-0 } = disp{13-0};
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}
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//===----------------------------------------------------------------------===//
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// Format #3 classes
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//
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// F3 - Common superclass of all F3 instructions. All instructions have an op3
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// field.
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class F3 : InstV9 {
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bits<6> op3;
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set op{1} = 1; // Op = 2 or 3
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set Inst{24-19} = op3;
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}
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// F3_rs1 - Common superclass of instructions that use rs1
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class F3_rs1 : F3 {
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bits<5> rs1;
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set Inst{18-14} = rs1;
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}
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// F3_rs1rd - Common superclass of instructions that use rs1 & rd...
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class F3_rs1rd : F3_rs1 {
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bits<5> rd;
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set Inst{29-25} = rd;
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}
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// F3_rs1rdrs2 - Common superclass of instructions with rs1, rd, & rs2 fields
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class F3_rs1rdrs2 : F3_rs1 {
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bits<5> rs2;
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set Inst{4-0} = rs2;
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}
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// Specific F3 classes...
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//
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class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rdrs2 {
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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set Inst{13} = 0; // i field = 0
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//set Inst{12-5} = dontcare;
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}
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class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rd {
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bits<13> simm;
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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set Inst{13} = 1; // i field = 1
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set Inst{12-0} = simm;
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}
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class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1 {
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bits<5> rs2;
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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//set Inst{29-25} = dontcare;
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set Inst{13} = 0;
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//set Inst{12-5} = dontcare;
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set Inst{4-0} = rs2;
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}
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class F3_4<bits<2> opVal, bits<6> op3val, string name> : F3_rs1 {
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bits<13> simm;
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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//set Inst{29-25} = dontcare;
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set Inst{13} = 1;
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set Inst{12-0} = simm;
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}
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class F3_16<bits<2> opVal, bits<6> op3val,
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bits<9> opfval, string name> : F3_rs1rdrs2 {
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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set Inst{13-5} = opfval;
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}
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class F3_18<bits<5> fcn, string name> : F3 {
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set op = 2;
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set op3 = 0b111110;
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set Name = name;
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set Inst{29-25} = fcn;
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//set Inst{18-0 } = dontcare;
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}
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//===----------------------------------------------------------------------===//
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// Instruction list...
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//
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// Section A.2: p161
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def ADDr : F3_1<2, 0b000000, "add">; // add r, r, r
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def ADDi : F3_2<2, 0b000000, "add">; // add r, r, i
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def ADDCCr : F3_1<2, 0b010000, "addcc">; // addcc r, r, r
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def ADDCCi : F3_2<2, 0b010000, "addcc">; // addcc r, r, i
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def ADDCr : F3_1<2, 0b001000, "addC">; // addC r, r, r
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def ADDCi : F3_2<2, 0b001000, "addC">; // addC r, r, i
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def ADDCCCr : F3_1<2, 0b011000, "addCcc">; // addCcc r, r, r
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def ADDCCCi : F3_2<2, 0b011000, "addCcc">; // addCcc r, r, i
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// Section A.3: p162
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set op2 = 0b011 in {
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def BRZ : F2_4<0b001, "brz">; // Branch on rs1 == 0
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def BRLEZ : F2_4<0b010, "brlez">; // Branch on rs1 <= 0
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def BRLZ : F2_4<0b011, "brlz">; // Branch on rs1 < 0
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def BRNZ : F2_4<0b101, "brnz">; // Branch on rs1 != 0
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def BRGZ : F2_4<0b110, "brgz">; // Branch on rs1 > 0
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def BRGEZ : F2_4<0b111, "brgez">; // Branch on rs1 >= 0
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}
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// Section A.4: p164
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set isDeprecated = 1 in {
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set op2 = 0b110 in {
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def FBA : F2_2<0b1000, "fba">; // Branch always
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def FBN : F2_2<0b0000, "fbn">; // Branch never
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def FBU : F2_2<0b0111, "fbu">; // Branch on unordered
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def FBG : F2_2<0b0110, "fbg">; // Branch >
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def FBUG : F2_2<0b0101, "fbug">; // Branch on unordered or >
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def FBL : F2_2<0b0100, "fbl">; // Branch <
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def FBUL : F2_2<0b0011, "fbul">; // Branch on unordered or <
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def FBLG : F2_2<0b0010, "fblg">; // Branch < or >
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def FBNE : F2_2<0b0001, "fbne">; // Branch !=
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def FBE : F2_2<0b1001, "fbe">; // Branch ==
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def FBUE : F2_2<0b1010, "fbue">; // Branch on unordered or ==
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def FBGE : F2_2<0b1011, "fbge">; // Branch > or ==
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def FBUGE : F2_2<0b1100, "fbuge">; // Branch unord or > or ==
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def FBLE : F2_2<0b1101, "fble">; // Branch < or ==
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def FBULE : F2_2<0b1110, "fbule">; // Branch unord or < or ==
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def FBO : F2_2<0b1111, "fbo">; // Branch on ordered
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}
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}
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// Section A.5: p167
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set op2 = 0b101 in {
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def FBPA : F2_3<0b1000, "fbpa">; // Branch always
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def FBPN : F2_3<0b0000, "fbpn">; // Branch never
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def FBPU : F2_3<0b0111, "fbpu">; // Branch on unordered
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def FBPG : F2_3<0b0110, "fbpg">; // Branch >
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def FBPUG : F2_3<0b0101, "fbpug">; // Branch on unordered or >
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def FBPL : F2_3<0b0100, "fbpl">; // Branch <
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def FBPUL : F2_3<0b0011, "fbpul">; // Branch on unordered or <
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def FBPLG : F2_3<0b0010, "fbplg">; // Branch < or >
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def FBPNE : F2_3<0b0001, "fbpne">; // Branch !=
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def FBPE : F2_3<0b1001, "fbpe">; // Branch ==
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def FBPUE : F2_3<0b1010, "fbpue">; // Branch on unordered or ==
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def FBPGE : F2_3<0b1011, "fbpge">; // Branch > or ==
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def FBPUGE : F2_3<0b1100, "fbpuge">; // Branch unord or > or ==
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def FBPLE : F2_3<0b1101, "fbple">; // Branch < or ==
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def FBPULE : F2_3<0b1110, "fbpule">; // Branch unord or < or ==
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def FBPO : F2_3<0b1111, "fbpo">; // Branch on ordered
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}
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// Section A.6: p170: Bicc
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set isDeprecated = 1 in {
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set op2 = 0b010 in {
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def BA : F2_2<0b1000, "ba">; // Branch always
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def BN : F2_2<0b0000, "bn">; // Branch never
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def BNE : F2_2<0b1001, "bne">; // Branch !=
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def BE : F2_2<0b0001, "be">; // Branch ==
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def BG : F2_2<0b1010, "bg">; // Branch >
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def BLE : F2_2<0b0010, "ble">; // Branch <=
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def BGE : F2_2<0b1011, "bge">; // Branch >=
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def BL : F2_2<0b0011, "bl">; // Branch <
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def BGU : F2_2<0b1100, "bgu">; // Branch unsigned >
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def BLEU : F2_2<0b0100, "bleu">; // Branch unsigned <=
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def BCC : F2_2<0b1101, "bcc">; // Branch unsigned >=
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def BCS : F2_2<0b0101, "bcs">; // Branch unsigned <=
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def BPOS : F2_2<0b1110, "bpos">; // Branch on positive
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def BNEG : F2_2<0b0110, "bneg">; // Branch on negative
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def BVC : F2_2<0b1111, "bvc">; // Branch on overflow clear
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def BVS : F2_2<0b0111, "bvs">; // Branch on overflow set
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}
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}
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// Section A.7: p172
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set op2 = 0b001 in {
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def BPA : F2_3<0b1000, "bpa">; // Branch always
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def BPN : F2_3<0b0000, "bpn">; // Branch never
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def BPNE : F2_3<0b1001, "bpne">; // Branch !=
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def BPE : F2_3<0b0001, "bpe">; // Branch ==
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def BPG : F2_3<0b1010, "bpg">; // Branch >
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def BPLE : F2_3<0b0010, "bple">; // Branch <=
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def BPGE : F2_3<0b1011, "bpge">; // Branch >=
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def BPL : F2_3<0b0011, "bpl">; // Branch <
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def BPGU : F2_3<0b1100, "bpgu">; // Branch unsigned >
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def BPLEU : F2_3<0b0100, "bpleu">; // Branch unsigned <=
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def BPCC : F2_3<0b1101, "bpcc">; // Branch unsigned >=
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def BPCS : F2_3<0b0101, "bpcs">; // Branch unsigned <=
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def BPPOS : F2_3<0b1110, "bppos">; // Branch on positive
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def BPNEG : F2_3<0b0110, "bpneg">; // Branch on negative
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def BPVC : F2_3<0b1111, "bpvc">; // Branch on overflow clear
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def BPVS : F2_3<0b0111, "bpvs">; // Branch on overflow set
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}
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// Section A.8: p175 - CALL - the only Format #1 instruction
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def CALL : InstV9 {
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bits<30> disp;
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set op = 1;
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set Inst{29-0} = disp;
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set Name = "call";
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set isCall = 1;
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}
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// Section A.9: Compare and Swap - p176
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// CASA/CASXA: are for alternate address spaces! Ignore them
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// Section A.10: Divide (64-bit / 32-bit) - p178
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set isDeprecated = 1 in {
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def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
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def UDIVi : F3_2<2, 0b001110, "udiv">; // udiv r, r, i
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def SDIVr : F3_1<2, 0b001111, "sdiv">; // sdiv r, r, r
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def SDIVi : F3_2<2, 0b001111, "sdiv">; // sdiv r, r, i
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def UDIVCCr : F3_1<2, 0b011110, "udivcc">; // udivcc r, r, r
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def UDIVCCi : F3_2<2, 0b011110, "udivcc">; // udivcc r, r, i
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def SDIVCCr : F3_1<2, 0b011111, "sdivcc">; // sdivcc r, r, r
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def SDIVCCi : F3_2<2, 0b011111, "sdivcc">; // sdivcc r, r, i
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}
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// Section A.11: DONE and RETRY - p181
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set isPrivileged = 1 in {
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def DONE : F3_18<0, "done">; // done
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def RETRY : F3_18<1, "retry">; // retry
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}
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// Section A.12: Floating-Point Add and Subtract - p182
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def FADDS : F3_16<2, 0b110100, 0x41, "fadds">; // fadds f, f, f
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def FADDD : F3_16<2, 0b110100, 0x42, "faddd">; // faddd f, f, f
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def FADDQ : F3_16<2, 0b110100, 0x43, "faddq">; // faddq f, f, f
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def FSUBS : F3_16<2, 0b110100, 0x45, "fsubs">; // fsubs f, f, f
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def FSUBD : F3_16<2, 0b110100, 0x46, "fsubd">; // fsubd f, f, f
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def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">; // fsubq f, f, f
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//
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// ...
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//
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// Section A.45: RETURN - p240
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set isReturn = 1 in {
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def RETURNr : F3_3<2, 0b111001, "return">; // return
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def RETURNi : F3_4<2, 0b111001, "return">; // return
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}
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