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Typo. 

llvm-svn: 231547
This commit is contained in:
Eric Christopher 2015-03-07 01:39:09 +00:00
parent e035e26655
commit 25dbdeb4d1
4 changed files with 4 additions and 4 deletions
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2
llvm/include/llvm/Analysis/TargetLibraryInfo.h
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@ -133,7 +133,7 @@ public:
return Impl->getLibFunc(funcName, F); return Impl->getLibFunc(funcName, F);
} }
/// \brief Tests wether a library function is available. /// \brief Tests whether a library function is available.
bool has(LibFunc::Func F) const { bool has(LibFunc::Func F) const {
return Impl->getState(F) != TargetLibraryInfoImpl::Unavailable; return Impl->getState(F) != TargetLibraryInfoImpl::Unavailable;
} }

2
llvm/include/llvm/DebugInfo/DWARF/DWARFFormValue.h
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@ -63,7 +63,7 @@ public:
/// The passed DWARFUnit is allowed to be nullptr, in which /// The passed DWARFUnit is allowed to be nullptr, in which
/// case no relocation processing will be performed and some /// case no relocation processing will be performed and some
/// kind of forms that depend on Unit information are disallowed. /// kind of forms that depend on Unit information are disallowed.
/// \returns wether the extraction succeeded. /// \returns whether the extraction succeeded.
bool extractValue(DataExtractor data, uint32_t *offset_ptr, bool extractValue(DataExtractor data, uint32_t *offset_ptr,
const DWARFUnit *u); const DWARFUnit *u);
bool isInlinedCStr() const { bool isInlinedCStr() const {

2
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
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@ -299,7 +299,7 @@ static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
} }
} }
/// \brief Determine wether it is worth to fold V into an extended register. /// \brief Determine whether it is worth to fold V into an extended register.
bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const { bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const {
// it hurts if the value is used at least twice, unless we are optimizing // it hurts if the value is used at least twice, unless we are optimizing
// for code size. // for code size.

2
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -9020,7 +9020,7 @@ static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
int LaneSize = Mask.size() / 2; int LaneSize = Mask.size() / 2;
// If there are only inputs from one 128-bit lane, splitting will in fact be // If there are only inputs from one 128-bit lane, splitting will in fact be
// less expensive. The flags track wether the given lane contains an element // less expensive. The flags track whether the given lane contains an element
// that crosses to another lane. // that crosses to another lane.
bool LaneCrossing[2] = {false, false}; bool LaneCrossing[2] = {false, false};
for (int i = 0, Size = Mask.size(); i < Size; ++i) for (int i = 0, Size = Mask.size(); i < Size; ++i)