forked from OSchip/llvm-project
[X86] Remove X86ISD::SHUF128 from combineBitcastForMaskedOp. Use isel patterns instead.
We always created X86ISD::SHUF128 with a 64-bit element type so we can use isel patterns to detect a bitconvert to 32-bit to handle masking. The test changes are because we also match the bitconvert even if there is no masking. This leads to unnecessary isel pattern, but it requires more multiclass hackery in tablegen to get rid of it. llvm-svn: 324205
This commit is contained in:
Craig Topper
parent
ec7029c286
commit
25ceba7f30
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@ -31395,15 +31395,6 @@ static bool combineBitcastForMaskedOp(SDValue OrigOp, SelectionDAG &DAG,
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unsigned Opcode = Op.getOpcode();
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switch (Opcode) {
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case X86ISD::SHUF128: {
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if (EltVT.getSizeInBits() != 32 && EltVT.getSizeInBits() != 64)
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return false;
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// Only change element size, not type.
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if (VT.isInteger() != Op.getSimpleValueType().isInteger())
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return false;
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return BitcastAndCombineShuffle(Opcode, Op.getOperand(0), Op.getOperand(1),
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Op.getOperand(2));
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}
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case X86ISD::SUBV_BROADCAST: {
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unsigned EltSize = EltVT.getSizeInBits();
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if (EltSize != 32 && EltSize != 64)
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@ -9361,25 +9361,60 @@ def : Pat<(v4f64 (ftrunc VR256X:$src)),
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(VRNDSCALEPDZ256rri VR256X:$src, (i32 0xB))>;
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}
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multiclass avx512_shuff_packed_128<string OpcodeStr, OpndItins itins,
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AVX512VLVectorVTInfo _, bits<8> opc>{
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let Predicates = [HasAVX512] in {
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defm Z : avx512_3Op_imm8<opc, OpcodeStr, X86Shuf128, itins, _.info512>, EVEX_V512;
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}
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let Predicates = [HasAVX512, HasVLX] in {
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defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, X86Shuf128, itins, _.info256>, EVEX_V256;
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multiclass avx512_shuff_packed_128_common<bits<8> opc, string OpcodeStr,
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OpndItins itins, X86VectorVTInfo _,
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X86VectorVTInfo CastInfo> {
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let ExeDomain = _.ExeDomain in {
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defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
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OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
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(_.VT (bitconvert
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(CastInfo.VT (X86Shuf128 _.RC:$src1, _.RC:$src2,
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(i8 imm:$src3))))),
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itins.rr>, Sched<[itins.Sched]>;
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defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
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OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
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(_.VT
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(bitconvert
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(CastInfo.VT (X86Shuf128 _.RC:$src1,
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(bitconvert (_.LdFrag addr:$src2)),
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(i8 imm:$src3))))), itins.rm>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
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OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
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"$src1, ${src2}"##_.BroadcastStr##", $src3",
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(_.VT
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(bitconvert
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(CastInfo.VT
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(X86Shuf128 _.RC:$src1,
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(X86VBroadcast (_.ScalarLdFrag addr:$src2)),
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(i8 imm:$src3))))), itins.rm>, EVEX_B,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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multiclass avx512_shuff_packed_128<string OpcodeStr, OpndItins itins,
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AVX512VLVectorVTInfo _,
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AVX512VLVectorVTInfo CastInfo, bits<8> opc>{
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let Predicates = [HasAVX512] in
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defm Z : avx512_shuff_packed_128_common<opc, OpcodeStr, itins,
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_.info512, CastInfo.info512>, EVEX_V512;
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let Predicates = [HasAVX512, HasVLX] in
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defm Z256 : avx512_shuff_packed_128_common<opc, OpcodeStr, itins,
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_.info256, CastInfo.info256>, EVEX_V256;
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}
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defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4", SSE_SHUFP,
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avx512vl_f32_info, 0x23>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
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avx512vl_f32_info, avx512vl_f64_info, 0x23>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
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defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2", SSE_SHUFP,
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avx512vl_f64_info, 0x23>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
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avx512vl_f64_info, avx512vl_f64_info, 0x23>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
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defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4", SSE_SHUFP,
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avx512vl_i32_info, 0x43>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
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avx512vl_i32_info, avx512vl_i64_info, 0x43>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
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defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2", SSE_SHUFP,
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avx512vl_i64_info, 0x43>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
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avx512vl_i64_info, avx512vl_i64_info, 0x43>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
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let Predicates = [HasAVX512] in {
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// Provide fallback in case the load node that is used in the broadcast
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@ -58,12 +58,12 @@ entry:
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define <16 x float> @test_mm512_shuffle_f32x4(<16 x float> %__A, <16 x float> %__B) {
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; X32-LABEL: test_mm512_shuffle_f32x4:
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; X32: # %bb.0: # %entry
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; X32-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[0,1,0,1]
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; X32-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[0,1,2,3,4,5,6,7],zmm1[0,1,2,3,0,1,2,3]
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; X32-NEXT: retl
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;
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; X64-LABEL: test_mm512_shuffle_f32x4:
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; X64: # %bb.0: # %entry
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; X64-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[0,1,0,1]
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; X64-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[0,1,2,3,4,5,6,7],zmm1[0,1,2,3,0,1,2,3]
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; X64-NEXT: retq
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entry:
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%shuffle = shufflevector <16 x float> %__A, <16 x float> %__B, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 16, i32 17, i32 18, i32 19>
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@ -9114,12 +9114,12 @@ define <8 x float> @test_8xfloat_zero_masked_shuff_mem_mask3(<8 x float> %vec1,
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define <16 x float> @test_16xfloat_shuff_mask0(<16 x float> %vec1, <16 x float> %vec2, <16 x i32> %mask) {
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; GENERIC-LABEL: test_16xfloat_shuff_mask0:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[6,7,0,1],zmm1[2,3,6,7] sched: [1:1.00]
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; GENERIC-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[12,13,14,15,0,1,2,3],zmm1[4,5,6,7,12,13,14,15] sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: test_16xfloat_shuff_mask0:
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; SKX: # %bb.0:
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; SKX-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[6,7,0,1],zmm1[2,3,6,7] sched: [3:1.00]
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; SKX-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[12,13,14,15,0,1,2,3],zmm1[4,5,6,7,12,13,14,15] sched: [3:1.00]
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; SKX-NEXT: retq # sched: [7:1.00]
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%res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>
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ret <16 x float> %res
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@ -9238,12 +9238,12 @@ define <16 x float> @test_16xfloat_zero_masked_shuff_mask2(<16 x float> %vec1, <
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define <16 x float> @test_16xfloat_shuff_mask3(<16 x float> %vec1, <16 x float> %vec2) {
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; GENERIC-LABEL: test_16xfloat_shuff_mask3:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[4,5,6,7],zmm1[0,1,4,5] sched: [1:1.00]
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; GENERIC-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[8,9,10,11,12,13,14,15],zmm1[0,1,2,3,8,9,10,11] sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: test_16xfloat_shuff_mask3:
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; SKX: # %bb.0:
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; SKX-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[4,5,6,7],zmm1[0,1,4,5] sched: [3:1.00]
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; SKX-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[8,9,10,11,12,13,14,15],zmm1[0,1,2,3,8,9,10,11] sched: [3:1.00]
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; SKX-NEXT: retq # sched: [7:1.00]
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%res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>
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ret <16 x float> %res
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@ -9288,12 +9288,12 @@ define <16 x float> @test_16xfloat_zero_masked_shuff_mask3(<16 x float> %vec1, <
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define <16 x float> @test_16xfloat_shuff_mem_mask0(<16 x float> %vec1, <16 x float>* %vec2p) {
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; GENERIC-LABEL: test_16xfloat_shuff_mem_mask0:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[6,7,4,5],mem[4,5,2,3] sched: [5:1.00]
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; GENERIC-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[12,13,14,15,8,9,10,11],mem[8,9,10,11,4,5,6,7] sched: [5:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: test_16xfloat_shuff_mem_mask0:
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; SKX: # %bb.0:
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; SKX-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[6,7,4,5],mem[4,5,2,3] sched: [10:1.00]
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; SKX-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[12,13,14,15,8,9,10,11],mem[8,9,10,11,4,5,6,7] sched: [10:1.00]
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; SKX-NEXT: retq # sched: [7:1.00]
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%vec2 = load <16 x float>, <16 x float>* %vec2p
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%res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>
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@ -9422,12 +9422,12 @@ define <16 x float> @test_16xfloat_zero_masked_shuff_mem_mask2(<16 x float> %vec
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define <16 x float> @test_16xfloat_shuff_mem_mask3(<16 x float> %vec1, <16 x float>* %vec2p) {
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; GENERIC-LABEL: test_16xfloat_shuff_mem_mask3:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[2,3,0,1],mem[6,7,6,7] sched: [5:1.00]
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; GENERIC-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,0,1,2,3],mem[12,13,14,15,12,13,14,15] sched: [5:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: test_16xfloat_shuff_mem_mask3:
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; SKX: # %bb.0:
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; SKX-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[2,3,0,1],mem[6,7,6,7] sched: [10:1.00]
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; SKX-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,0,1,2,3],mem[12,13,14,15,12,13,14,15] sched: [10:1.00]
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; SKX-NEXT: retq # sched: [7:1.00]
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%vec2 = load <16 x float>, <16 x float>* %vec2p
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%res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>
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@ -10562,12 +10562,12 @@ define <8 x i32> @test_8xi32_zero_masked_shuff_mem_mask3(<8 x i32> %vec1, <8 x i
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define <16 x i32> @test_16xi32_shuff_mask0(<16 x i32> %vec1, <16 x i32> %vec2) {
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; GENERIC-LABEL: test_16xi32_shuff_mask0:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,2,3],zmm1[2,3,6,7] sched: [1:1.00]
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; GENERIC-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,4,5,6,7],zmm1[4,5,6,7,12,13,14,15] sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: test_16xi32_shuff_mask0:
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; SKX: # %bb.0:
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; SKX-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,2,3],zmm1[2,3,6,7] sched: [3:1.00]
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; SKX-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,4,5,6,7],zmm1[4,5,6,7,12,13,14,15] sched: [3:1.00]
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; SKX-NEXT: retq # sched: [7:1.00]
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%res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>
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ret <16 x i32> %res
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@ -10686,12 +10686,12 @@ define <16 x i32> @test_16xi32_zero_masked_shuff_mask2(<16 x i32> %vec1, <16 x i
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define <16 x i32> @test_16xi32_shuff_mask3(<16 x i32> %vec1, <16 x i32> %vec2) {
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; GENERIC-LABEL: test_16xi32_shuff_mask3:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,0,1],zmm1[4,5,2,3] sched: [1:1.00]
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; GENERIC-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,0,1,2,3],zmm1[8,9,10,11,4,5,6,7] sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: test_16xi32_shuff_mask3:
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; SKX: # %bb.0:
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; SKX-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,0,1],zmm1[4,5,2,3] sched: [3:1.00]
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; SKX-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,0,1,2,3],zmm1[8,9,10,11,4,5,6,7] sched: [3:1.00]
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; SKX-NEXT: retq # sched: [7:1.00]
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%res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>
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ret <16 x i32> %res
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@ -10736,12 +10736,12 @@ define <16 x i32> @test_16xi32_zero_masked_shuff_mask3(<16 x i32> %vec1, <16 x i
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define <16 x i32> @test_16xi32_shuff_mem_mask0(<16 x i32> %vec1, <16 x i32>* %vec2p) {
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; GENERIC-LABEL: test_16xi32_shuff_mem_mask0:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[4,5,2,3],mem[4,5,0,1] sched: [5:1.00]
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; GENERIC-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[8,9,10,11,4,5,6,7],mem[8,9,10,11,0,1,2,3] sched: [5:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: test_16xi32_shuff_mem_mask0:
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; SKX: # %bb.0:
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; SKX-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[4,5,2,3],mem[4,5,0,1] sched: [10:1.00]
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; SKX-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[8,9,10,11,4,5,6,7],mem[8,9,10,11,0,1,2,3] sched: [10:1.00]
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; SKX-NEXT: retq # sched: [7:1.00]
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%vec2 = load <16 x i32>, <16 x i32>* %vec2p
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%res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 16, i32 17, i32 18, i32 19>
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@ -10870,12 +10870,12 @@ define <16 x i32> @test_16xi32_zero_masked_shuff_mem_mask2(<16 x i32> %vec1, <16
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define <16 x i32> @test_16xi32_shuff_mem_mask3(<16 x i32> %vec1, <16 x i32>* %vec2p) {
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; GENERIC-LABEL: test_16xi32_shuff_mem_mask3:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,2,3],mem[2,3,6,7] sched: [5:1.00]
|
||||
; GENERIC-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,4,5,6,7],mem[4,5,6,7,12,13,14,15] sched: [5:1.00]
|
||||
; GENERIC-NEXT: retq # sched: [1:1.00]
|
||||
;
|
||||
; SKX-LABEL: test_16xi32_shuff_mem_mask3:
|
||||
; SKX: # %bb.0:
|
||||
; SKX-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,2,3],mem[2,3,6,7] sched: [10:1.00]
|
||||
; SKX-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,4,5,6,7],mem[4,5,6,7,12,13,14,15] sched: [10:1.00]
|
||||
; SKX-NEXT: retq # sched: [7:1.00]
|
||||
%vec2 = load <16 x i32>, <16 x i32>* %vec2p
|
||||
%res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>
|
||||
|
|
|
|||
|
|
@ -260,7 +260,7 @@ define <8 x float> @test_8xfloat_zero_masked_shuff_mem_mask3(<8 x float> %vec1,
|
|||
define <16 x float> @test_16xfloat_shuff_mask0(<16 x float> %vec1, <16 x float> %vec2) {
|
||||
; CHECK-LABEL: test_16xfloat_shuff_mask0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[6,7,0,1],zmm1[2,3,6,7]
|
||||
; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[12,13,14,15,0,1,2,3],zmm1[4,5,6,7,12,13,14,15]
|
||||
; CHECK-NEXT: retq
|
||||
%res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>
|
||||
ret <16 x float> %res
|
||||
|
|
@ -346,7 +346,7 @@ define <16 x float> @test_16xfloat_zero_masked_shuff_mask2(<16 x float> %vec1, <
|
|||
define <16 x float> @test_16xfloat_shuff_mask3(<16 x float> %vec1, <16 x float> %vec2) {
|
||||
; CHECK-LABEL: test_16xfloat_shuff_mask3:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[4,5,6,7],zmm1[0,1,4,5]
|
||||
; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[8,9,10,11,12,13,14,15],zmm1[0,1,2,3,8,9,10,11]
|
||||
; CHECK-NEXT: retq
|
||||
%res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>
|
||||
ret <16 x float> %res
|
||||
|
|
@ -380,7 +380,7 @@ define <16 x float> @test_16xfloat_zero_masked_shuff_mask3(<16 x float> %vec1, <
|
|||
define <16 x float> @test_16xfloat_shuff_mem_mask0(<16 x float> %vec1, <16 x float>* %vec2p) {
|
||||
; CHECK-LABEL: test_16xfloat_shuff_mem_mask0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[6,7,4,5],mem[4,5,2,3]
|
||||
; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[12,13,14,15,8,9,10,11],mem[8,9,10,11,4,5,6,7]
|
||||
; CHECK-NEXT: retq
|
||||
%vec2 = load <16 x float>, <16 x float>* %vec2p
|
||||
%res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>
|
||||
|
|
@ -476,7 +476,7 @@ define <16 x float> @test_16xfloat_zero_masked_shuff_mem_mask2(<16 x float> %vec
|
|||
define <16 x float> @test_16xfloat_shuff_mem_mask3(<16 x float> %vec1, <16 x float>* %vec2p) {
|
||||
; CHECK-LABEL: test_16xfloat_shuff_mem_mask3:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[2,3,0,1],mem[6,7,6,7]
|
||||
; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,0,1,2,3],mem[12,13,14,15,12,13,14,15]
|
||||
; CHECK-NEXT: retq
|
||||
%vec2 = load <16 x float>, <16 x float>* %vec2p
|
||||
%res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>
|
||||
|
|
@ -1260,7 +1260,7 @@ define <8 x i32> @test_8xi32_zero_masked_shuff_mem_mask3(<8 x i32> %vec1, <8 x i
|
|||
define <16 x i32> @test_16xi32_shuff_mask0(<16 x i32> %vec1, <16 x i32> %vec2) {
|
||||
; CHECK-LABEL: test_16xi32_shuff_mask0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,2,3],zmm1[2,3,6,7]
|
||||
; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,4,5,6,7],zmm1[4,5,6,7,12,13,14,15]
|
||||
; CHECK-NEXT: retq
|
||||
%res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>
|
||||
ret <16 x i32> %res
|
||||
|
|
@ -1340,7 +1340,7 @@ define <16 x i32> @test_16xi32_zero_masked_shuff_mask2(<16 x i32> %vec1, <16 x i
|
|||
define <16 x i32> @test_16xi32_shuff_mask3(<16 x i32> %vec1, <16 x i32> %vec2) {
|
||||
; CHECK-LABEL: test_16xi32_shuff_mask3:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,0,1],zmm1[4,5,2,3]
|
||||
; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,0,1,2,3],zmm1[8,9,10,11,4,5,6,7]
|
||||
; CHECK-NEXT: retq
|
||||
%res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>
|
||||
ret <16 x i32> %res
|
||||
|
|
@ -1372,7 +1372,7 @@ define <16 x i32> @test_16xi32_zero_masked_shuff_mask3(<16 x i32> %vec1, <16 x i
|
|||
define <16 x i32> @test_16xi32_shuff_mem_mask0(<16 x i32> %vec1, <16 x i32>* %vec2p) {
|
||||
; CHECK-LABEL: test_16xi32_shuff_mem_mask0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[4,5,2,3],mem[4,5,0,1]
|
||||
; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[8,9,10,11,4,5,6,7],mem[8,9,10,11,0,1,2,3]
|
||||
; CHECK-NEXT: retq
|
||||
%vec2 = load <16 x i32>, <16 x i32>* %vec2p
|
||||
%res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 16, i32 17, i32 18, i32 19>
|
||||
|
|
@ -1462,7 +1462,7 @@ define <16 x i32> @test_16xi32_zero_masked_shuff_mem_mask2(<16 x i32> %vec1, <16
|
|||
define <16 x i32> @test_16xi32_shuff_mem_mask3(<16 x i32> %vec1, <16 x i32>* %vec2p) {
|
||||
; CHECK-LABEL: test_16xi32_shuff_mem_mask3:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,2,3],mem[2,3,6,7]
|
||||
; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[4,5,6,7,4,5,6,7],mem[4,5,6,7,12,13,14,15]
|
||||
; CHECK-NEXT: retq
|
||||
%vec2 = load <16 x i32>, <16 x i32>* %vec2p
|
||||
%res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>
|
||||
|
|
|
|||
|
|
@ -547,7 +547,7 @@ define <16 x i32> @maskz_shuffle_v16i32_02_03_04_05_06_07_08_09_10_11_12_13_14_1
|
|||
define <16 x float> @test_vshuff32x4_512(<16 x float> %x, <16 x float> %x1) nounwind {
|
||||
; ALL-LABEL: test_vshuff32x4_512:
|
||||
; ALL: # %bb.0:
|
||||
; ALL-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[2,3,0,1]
|
||||
; ALL-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[0,1,2,3,4,5,6,7],zmm1[4,5,6,7,0,1,2,3]
|
||||
; ALL-NEXT: retq
|
||||
%res = shufflevector <16 x float> %x, <16 x float> %x1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 16, i32 17, i32 18, i32 19>
|
||||
ret <16 x float> %res
|
||||
|
|
@ -556,7 +556,7 @@ define <16 x float> @test_vshuff32x4_512(<16 x float> %x, <16 x float> %x1) noun
|
|||
define <16 x i32> @test_vshufi32x4_512(<16 x i32> %x, <16 x i32> %x1) nounwind {
|
||||
; ALL-LABEL: test_vshufi32x4_512:
|
||||
; ALL: # %bb.0:
|
||||
; ALL-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[2,3,0,1]
|
||||
; ALL-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[0,1,2,3,4,5,6,7],zmm1[4,5,6,7,0,1,2,3]
|
||||
; ALL-NEXT: retq
|
||||
%res = shufflevector <16 x i32> %x, <16 x i32> %x1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 16, i32 17, i32 18, i32 19>
|
||||
ret <16 x i32> %res
|
||||
|
|
|
|||
Loading…
Reference in New Issue