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[mips] Marked the ADDi instruction aliases as not available in Mips32R6 and Mips64R6. 

Patch by Vasileios Kalintiris.

Differential Revision: http://reviews.llvm.org/D5242

llvm-svn: 217867
This commit is contained in:
Toma Tabacu 2014-09-16 09:26:09 +00:00
parent 8e72eb780e
commit 25cdd222b0
13 changed files with 51 additions and 6 deletions
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3
llvm/lib/Target/Mips/Mips64InstrInfo.td
View File

@ -452,9 +452,6 @@ def : MipsInstAlias<"daddu $rs, $imm",
def : MipsInstAlias<"dadd $rs, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
0>, ISA_MIPS3_NOT_32R6_64R6;
def : MipsInstAlias<"add $rs, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
0>;
def : MipsInstAlias<"addu $rs, $imm",
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
0>;

10
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -1437,7 +1437,11 @@ def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
def : MipsInstAlias<"addu $rs, $rt, $imm",
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
def : MipsInstAlias<"add $rs, $rt, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"add $rs, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"and $rs, $rt, $imm",
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
def : MipsInstAlias<"and $rs, $imm",
@ -1501,10 +1505,10 @@ def : MipsInstAlias<"sll $rd, $rt, $rs",
(SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sub, $rd, $rs, $imm",
(ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
InvertedImOperand:$imm), 0>;
InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"sub $rs, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
0>;
0>, ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"subu, $rd, $rs, $imm",
(ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
InvertedImOperand:$imm), 0>;

4
llvm/test/MC/Mips/mips1/valid.s
View File

@ -10,6 +10,8 @@
add.s $f8,$f21,$f24
addi $13,$9,26322
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
addu $9,$a0,$a2
and $s7,$v0,$12
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
@ -97,6 +99,8 @@
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6

4
llvm/test/MC/Mips/mips2/valid.s
View File

@ -6,6 +6,8 @@
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29
add.s $f8,$f21,$f24
addi $13,$9,26322
@ -113,6 +115,8 @@
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6

4
llvm/test/MC/Mips/mips3/valid.s
View File

@ -6,6 +6,8 @@
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29
add.s $f8,$f21,$f24
addi $13,$9,26322
@ -175,6 +177,8 @@
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6

4
llvm/test/MC/Mips/mips32/valid.s
View File

@ -6,6 +6,8 @@
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29
add.s $f8,$f21,$f24
addi $13,$9,26322
@ -141,6 +143,8 @@
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6

4
llvm/test/MC/Mips/mips32r2/valid.s
View File

@ -6,6 +6,8 @@
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29
add.s $f8,$f21,$f24
addi $13,$9,26322
@ -169,6 +171,8 @@
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6

4
llvm/test/MC/Mips/mips32r6/invalid-mips1.s
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@ -5,6 +5,8 @@
# RUN: FileCheck %s < %t1
.set noat
add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
@ -22,3 +24,5 @@
multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
# div has been re-encoded. See valid.s
# divu has been re-encoded. See valid.s
sub $22,$17,-3126 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sub $13,6512 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

4
llvm/test/MC/Mips/mips4/valid.s
View File

@ -6,6 +6,8 @@
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29
add.s $f8,$f21,$f24
addi $13,$9,26322
@ -193,6 +195,8 @@
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6

4
llvm/test/MC/Mips/mips5/valid.s
View File

@ -6,6 +6,8 @@
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29
add.s $f8,$f21,$f24
addi $13,$9,26322
@ -194,6 +196,8 @@
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6

4
llvm/test/MC/Mips/mips64/valid.s
View File

@ -6,6 +6,8 @@
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29
add.s $f8,$f21,$f24
addi $13,$9,26322
@ -210,6 +212,8 @@
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6

4
llvm/test/MC/Mips/mips64r2/valid.s
View File

@ -6,6 +6,8 @@
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
add $s7,$s2,$a1
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
add.d $f1,$f7,$f29
add.s $f8,$f21,$f24
addi $13,$9,26322
@ -237,6 +239,8 @@
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
sub.d $f18,$f3,$f17
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6

4
llvm/test/MC/Mips/mips64r6/invalid-mips1.s
View File

@ -5,6 +5,8 @@
# RUN: FileCheck %s < %t1
.set noat
add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
@ -25,3 +27,5 @@
multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
# div has been re-encoded. See valid.s
# divu has been re-encoded. See valid.s
sub $22,$17,-3126 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sub $13,6512 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled