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[FPEnv][AArch64] Add lowering and instruction selection for STRICT_FP_ROUND 

This gets selected to the appropriate fcvt instruction. Handling from there on
isn't fully correct yet, as we need to model fcvt reading and writing to fpsr
and fpcr.

Differential Revision: https://reviews.llvm.org/D73201
This commit is contained in:
John Brawn 2020-01-21 17:18:18 +00:00
parent 727ed11b24
commit 258d8dd76a
3 changed files with 34 additions and 11 deletions
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18
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -293,6 +293,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
// Variable arguments.
setOperationAction(ISD::VASTART, MVT::Other, Custom);
@ -2521,21 +2523,26 @@ SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
SelectionDAG &DAG) const {
if (Op.getOperand(0).getValueType() != MVT::f128) {
bool IsStrict = Op->isStrictFPOpcode();
SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
if (SrcVal.getValueType() != MVT::f128) {
// It's legal except when f128 is involved
return Op;
}
RTLIB::Libcall LC;
LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
LC = RTLIB::getFPROUND(SrcVal.getValueType(), Op.getValueType());
// FP_ROUND node has a second operand indicating whether it is known to be
// precise. That doesn't take part in the LibCall so we can't directly use
// LowerF128Call.
SDValue SrcVal = Op.getOperand(0);
MakeLibCallOptions CallOptions;
return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, CallOptions,
SDLoc(Op)).first;
SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
SDValue Result;
SDLoc dl(Op);
std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
CallOptions, dl, Chain);
return IsStrict ? DAG.getMergeValues({Result, Chain}, dl) : Result;
}
SDValue AArch64TargetLowering::LowerVectorFP_TO_INT(SDValue Op,
@ -3210,6 +3217,7 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
case ISD::FDIV:
return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
case ISD::FP_ROUND:
case ISD::STRICT_FP_ROUND:
return LowerFP_ROUND(Op, DAG);
case ISD::FP_EXTEND:
return LowerFP_EXTEND(Op, DAG);

6
llvm/lib/Target/AArch64/AArch64InstrFormats.td
View File

@ -4736,11 +4736,11 @@ class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
multiclass FPConversion<string asm> {
// Double-precision to Half-precision
def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
[(set FPR16:$Rd, (fpround FPR64:$Rn))]>;
[(set FPR16:$Rd, (any_fpround FPR64:$Rn))]>;
// Double-precision to Single-precision
def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
[(set FPR32:$Rd, (fpround FPR64:$Rn))]>;
[(set FPR32:$Rd, (any_fpround FPR64:$Rn))]>;
// Half-precision to Double-precision
def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
@ -4756,7 +4756,7 @@ multiclass FPConversion<string asm> {
// Single-precision to Half-precision
def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
[(set FPR16:$Rd, (fpround FPR32:$Rn))]>;
[(set FPR16:$Rd, (any_fpround FPR32:$Rn))]>;
}
//---

21
llvm/test/CodeGen/AArch64/fp-intrinsics.ll
View File

@ -77,9 +77,19 @@ define i64 @fptoui_i64_f32(float %x) #0 {
ret i64 %val
}
; TODO: sitofp_f32_i32 (missing STRICT_FP_ROUND handling)
; CHECK-LABEL: sitofp_f32_i32:
; FIXME-CHECK: scvtf s0, w0
define float @sitofp_f32_i32(i32 %x) #0 {
%val = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret float %val
}
; TODO: uitofp_f32_i32 (missing STRICT_FP_ROUND handling)
; CHECK-LABEL: uitofp_f32_i32:
; FIXME-CHECK: ucvtf s0, w0
define float @uitofp_f32_i32(i32 %x) #0 {
%val = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret float %val
}
; TODO: sitofp_f32_i64 (missing STRICT_SINT_TO_FP handling)
@ -880,7 +890,12 @@ define i32 @fcmps_une_f64(double %a, double %b) #0 {
; Single/Double conversion intrinsics
; TODO: fptrunc_f32 (missing STRICT_FP_ROUND handling)
; CHECK-LABEL: fptrunc_f32:
; CHECK: fcvt s0, d0
define float @fptrunc_f32(double %x) #0 {
%val = call float @llvm.experimental.constrained.fptrunc.f32.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret float %val
}
; CHECK-LABEL: fpext_f32:
; CHECK: fcvt d0, s0