From 25883487a11698400a8b45c8a3325545e74a03ac Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Tue, 5 Apr 2011 21:49:44 +0000 Subject: [PATCH] ARM disassembler was erroneously accepting an invalid LSL instruction. For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941 --- llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 4 ++++ llvm/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt | 9 +++++++++ 2 files changed, 13 insertions(+) create mode 100644 llvm/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 9ba4a8d62459..786e001127f3 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1068,6 +1068,10 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRm(insn)))); if (Rs) { + // If Inst{7} != 0, we should reject this insn as an invalid encoding. + if (slice(insn, 7, 7)) + return false; + // Register-controlled shifts: [Rm, Rs, shift]. MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRs(insn)))); diff --git a/llvm/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt new file mode 100644 index 000000000000..3165ff794f97 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# A8.6.89 LSL (register): Inst{7-4} = 0b0001 +0x93 0x42 0xa0 0xd1