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CodeGen: Use LLT instead of EVT in getRegisterByName 

Only PPC seems to be using it, and only checks some simple cases and
doesn't distinguish between FP. Just switch to using LLT to simplify
use from GlobalISel.
This commit is contained in:
Matt Arsenault 2019-12-28 09:18:56 -05:00 committed by Matt Arsenault
parent cc95bb1f57
commit 255cc5a760
22 changed files with 32 additions and 27 deletions
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2
llvm/include/llvm/CodeGen/TargetLowering.h
View File

@ -3710,7 +3710,7 @@ public:
/// Return the register ID of the name passed in. Used by named register
/// global variables extension. There is no target-independent behaviour
/// so the default action is to bail.
virtual Register getRegisterByName(const char* RegName, EVT VT,
virtual Register getRegisterByName(const char* RegName, LLT Ty,
const MachineFunction &MF) const {
report_fatal_error("Named registers not implemented for this target");
}

12
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -2251,8 +2251,11 @@ void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
SDLoc dl(Op);
MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
EVT VT = Op->getValueType(0);
LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
Register Reg =
TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0),
TLI->getRegisterByName(RegStr->getString().data(), Ty,
CurDAG->getMachineFunction());
SDValue New = CurDAG->getCopyFromReg(
Op->getOperand(0), dl, Reg, Op->getValueType(0));
@ -2265,8 +2268,11 @@ void SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
SDLoc dl(Op);
MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
Register Reg = TLI->getRegisterByName(RegStr->getString().data(),
Op->getOperand(2).getValueType(),
EVT VT = Op->getOperand(2).getValueType();
LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty,
CurDAG->getMachineFunction());
SDValue New = CurDAG->getCopyToReg(
Op->getOperand(0), dl, Reg, Op->getOperand(2));

2
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -5667,7 +5667,7 @@ SDValue AArch64TargetLowering::LowerSPONENTRY(SDValue Op,
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
Register AArch64TargetLowering::
getRegisterByName(const char* RegName, EVT VT, const MachineFunction &MF) const {
getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const {
Register Reg = MatchRegisterName(RegName);
if (AArch64::X1 <= Reg && Reg <= AArch64::X28) {
const MCRegisterInfo *MRI = Subtarget->getRegisterInfo();

2
llvm/lib/Target/AArch64/AArch64ISelLowering.h
View File

@ -761,7 +761,7 @@ private:
unsigned combineRepeatedFPDivisors() const override;
ConstraintType getConstraintType(StringRef Constraint) const override;
Register getRegisterByName(const char* RegName, EVT VT,
Register getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const override;
/// Examine constraint string and operand type and determine a weight value.

2
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -2990,7 +2990,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
IsThisReturn ? OutVals[0] : SDValue());
}
Register SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
Register SITargetLowering::getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const {
Register Reg = StringSwitch<Register>(RegName)
.Case("m0", AMDGPU::M0)

2
llvm/lib/Target/AMDGPU/SIISelLowering.h
View File

@ -330,7 +330,7 @@ public:
SDValue LowerCall(CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const override;
Register getRegisterByName(const char* RegName, EVT VT,
Register getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const override;
MachineBasicBlock *splitKillBlock(MachineInstr &MI,

2
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -5614,7 +5614,7 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
Register ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const {
Register Reg = StringSwitch<unsigned>(RegName)
.Case("sp", ARM::SP)

2
llvm/lib/Target/ARM/ARMISelLowering.h
View File

@ -738,7 +738,7 @@ class VectorType;
void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const;
Register getRegisterByName(const char* RegName, EVT VT,
Register getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const override;
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,

2
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -237,7 +237,7 @@ bool HexagonTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
}
Register HexagonTargetLowering::getRegisterByName(
const char* RegName, EVT VT, const MachineFunction &) const {
const char* RegName, LLT VT, const MachineFunction &) const {
// Just support r19, the linux kernel uses it.
Register Reg = StringSwitch<Register>(RegName)
.Case("r0", Hexagon::R0)

2
llvm/lib/Target/Hexagon/HexagonISelLowering.h
View File

@ -230,7 +230,7 @@ namespace HexagonISD {
bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
Register getRegisterByName(const char* RegName, EVT VT,
Register getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const override;
/// If a physical register, this returns the register that receives the

2
llvm/lib/Target/Lanai/LanaiISelLowering.cpp
View File

@ -213,7 +213,7 @@ SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
//===----------------------------------------------------------------------===//
Register LanaiTargetLowering::getRegisterByName(
const char *RegName, EVT /*VT*/,
const char *RegName, LLT /*VT*/,
const MachineFunction & /*MF*/) const {
// Only unallocatable registers should be matched here.
Register Reg = StringSwitch<unsigned>(RegName)

2
llvm/lib/Target/Lanai/LanaiISelLowering.h
View File

@ -90,7 +90,7 @@ public:
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
Register getRegisterByName(const char *RegName, EVT VT,
Register getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const override;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,

2
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -4689,7 +4689,7 @@ MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
Register
MipsTargetLowering::getRegisterByName(const char *RegName, EVT VT,
MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const {
// Named registers is expected to be fairly rare. For now, just support $28
// since the linux kernel uses it.

2
llvm/lib/Target/Mips/MipsISelLowering.h
View File

@ -348,7 +348,7 @@ class TargetRegisterClass;
void HandleByVal(CCState *, unsigned &, unsigned) const override;
Register getRegisterByName(const char* RegName, EVT VT,
Register getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const override;
/// If a physical register, this returns the register that receives the

7
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -14792,16 +14792,15 @@ SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
Register PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
Register PPCTargetLowering::getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const {
bool isPPC64 = Subtarget.isPPC64();
bool IsDarwinABI = Subtarget.isDarwinABI();
if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
(!isPPC64 && VT != MVT::i32))
bool is64Bit = isPPC64 && VT == LLT::scalar(64);
if (!is64Bit && VT != LLT::scalar(32))
report_fatal_error("Invalid register global variable type");
bool is64Bit = isPPC64 && VT == MVT::i64;
Register Reg = StringSwitch<Register>(RegName)
.Case("r1", is64Bit ? PPC::X1 : PPC::R1)
.Case("r2", (IsDarwinABI || isPPC64) ? Register() : PPC::R2)

2
llvm/lib/Target/PowerPC/PPCISelLowering.h
View File

@ -752,7 +752,7 @@ namespace llvm {
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
SmallVectorImpl<SDNode *> &Created) const override;
Register getRegisterByName(const char* RegName, EVT VT,
Register getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const override;
void computeKnownBitsForTargetNode(const SDValue Op,

2
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -2893,7 +2893,7 @@ bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const {
#include "RISCVGenAsmMatcher.inc"
Register
RISCVTargetLowering::getRegisterByName(const char *RegName, EVT VT,
RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const {
Register Reg = MatchRegisterAltName(RegName);
if (Reg == RISCV::NoRegister)

2
llvm/lib/Target/RISCV/RISCVISelLowering.h
View File

@ -151,7 +151,7 @@ public:
/// method is necessary to lower the llvm.read_register.* and
/// llvm.write_register.* intrinsics. Allocatable registers must be reserved
/// with the clang -ffixed-xX flag for access to be allowed.
Register getRegisterByName(const char *RegName, EVT VT,
Register getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const override;
private:

2
llvm/lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -1016,7 +1016,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
Register SparcTargetLowering::getRegisterByName(const char* RegName, EVT VT,
Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const {
Register Reg = StringSwitch<unsigned>(RegName)
.Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)

2
llvm/lib/Target/Sparc/SparcISelLowering.h
View File

@ -98,7 +98,7 @@ namespace llvm {
return MVT::i32;
}
Register getRegisterByName(const char* RegName, EVT VT,
Register getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const override;
/// If a physical register, this returns the register that receives the

2
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -25046,7 +25046,7 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
Register X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
Register X86TargetLowering::getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const {
const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();

2
llvm/lib/Target/X86/X86ISelLowering.h
View File

@ -1189,7 +1189,7 @@ namespace llvm {
return nullptr; // nothing to do, move along.
}
Register getRegisterByName(const char* RegName, EVT VT,
Register getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const override;
/// If a physical register, this returns the register that receives the