forked from OSchip/llvm-project
[PowerPC] Enable CR bits support for Power8 and above.
This patch turns on support for CR bit accesses for Power8 and above. The reason why CR bits are turned on as the default for Power8 and above is that because later architectures make use of builtins and instructions that require CR bit accesses (such as the use of setbc in the vector string isolate predicate and bcd builtins on Power10). This patch also adds the clang portion to allow for turning on CR bits in the front end if the user so desires to. Differential Revision: https://reviews.llvm.org/D124060
This commit is contained in:
Amy Kwan
parent
3d09c9b30f
commit
2534dc120a
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@ -3575,6 +3575,8 @@ PowerPC
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.. option:: -mcrbits, -mno-crbits
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Control the CR-bit tracking feature on PowerPC. ``-mcrbits`` (the enablement of CR-bit tracking support) is the default for POWER8 and above, as well as for all other CPUs when optimization is applied (-O2 and above).
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.. option:: -mcrypto, -mno-crypto
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.. option:: -mdirect-move, -mno-direct-move
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@ -36,6 +36,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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HasAltivec = true;
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} else if (Feature == "+vsx") {
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HasVSX = true;
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} else if (Feature == "+crbits") {
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UseCRBits = true;
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} else if (Feature == "+bpermd") {
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HasBPERMD = true;
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} else if (Feature == "+extdiv") {
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@ -515,6 +517,11 @@ bool PPCTargetInfo::initFeatureMap(
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.Case("pwr9", true)
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.Case("pwr8", true)
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.Default(false);
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Features["crbits"] = llvm::StringSwitch<bool>(CPU)
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.Case("ppc64le", true)
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.Case("pwr9", true)
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.Case("pwr8", true)
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.Default(false);
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Features["vsx"] = llvm::StringSwitch<bool>(CPU)
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.Case("ppc64le", true)
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.Case("pwr9", true)
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@ -649,6 +656,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
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.Case("powerpc", true)
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.Case("altivec", HasAltivec)
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.Case("vsx", HasVSX)
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.Case("crbits", UseCRBits)
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.Case("power8-vector", HasP8Vector)
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.Case("crypto", HasP8Crypto)
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.Case("direct-move", HasDirectMove)
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@ -62,6 +62,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
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bool HasROPProtect = false;
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bool HasPrivileged = false;
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bool HasVSX = false;
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bool UseCRBits = false;
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bool HasP8Vector = false;
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bool HasP8Crypto = false;
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bool HasDirectMove = false;
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@ -0,0 +1,112 @@
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// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr10 \
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// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
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// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr10 \
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// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
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// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr9 \
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// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
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// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr9 \
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// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
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// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr8 \
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// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
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// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr8 \
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// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
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// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr7 \
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// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
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// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr7 \
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// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
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// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr10 \
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// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
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// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr10 \
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// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
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// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr9 \
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// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
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// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr9 \
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// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
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// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr8 \
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// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
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// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr8 \
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// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
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// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr7 \
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// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
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// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr7 \
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// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
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// CHECK-NOCRBITS: "-target-feature" "-crbits"
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// CHECK-CRBITS: "-target-feature" "+crbits"
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -emit-llvm \
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// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -mcrbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -mno-crbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr9 -emit-llvm \
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// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr9 -mcrbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr9 -mno-crbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -emit-llvm \
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// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mcrbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mno-crbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -emit-llvm \
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// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mcrbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mno-crbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr10 -emit-llvm \
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// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr10 -mcrbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr10 -mno-crbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr9 -emit-llvm \
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// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr9 -mcrbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr9 -mno-crbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr8 -emit-llvm \
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// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr8 -mcrbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr8 -mno-crbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -emit-llvm \
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// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -mcrbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
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// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -mno-crbits \
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// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
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// HAS-CRBITS: main(
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// HAS-CRBITS: attributes #0 = {
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// HAS-CRBITS-SAME: +crbits
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// HAS-NOCRBITS: main(
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// HAS-NOCRBITS: attributes #0 = {
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// HAS-NOCRBITS-SAME: -crbits
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int main(int argc, char *argv[]) {
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return 0;
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}
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@ -376,7 +376,8 @@ def ProcessorFeatures {
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FeaturePartwordAtomic,
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FeatureQuadwordAtomic,
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FeaturePredictableSelectIsExpensive,
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FeatureISA2_07
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FeatureISA2_07,
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FeatureCRBits
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];
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list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
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@ -23,12 +23,11 @@ define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* n
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; CHECK-NEXT: addc 6, 6, 7
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; CHECK-NEXT: addze 5, 5
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; CHECK-NEXT: add 3, 5, 3
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; CHECK-NEXT: cmpld 7, 3, 5
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; CHECK-NEXT: mfocrf 3, 1
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; CHECK-NEXT: rlwinm 5, 3, 29, 31, 31
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; CHECK-NEXT: # implicit-def: $x3
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; CHECK-NEXT: mr 3, 5
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: cmpld 3, 5
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; CHECK-NEXT: crmove 20, 0
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: isel 3, 3, 5, 20
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; CHECK-NEXT: std 3, 0(4)
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; CHECK-NEXT: blr
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%1 = load i64, i64* %a, align 8
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@ -14,10 +14,6 @@ define i32 @test_choice1(fp128 %a, fp128 %b) #0 {
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; P8-NEXT: nop
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; P8-NEXT: # kill: def $r3 killed $r3 killed $x3
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; P8-NEXT: cmplwi 3, 0
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; P8-NEXT: li 3, 0
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; P8-NEXT: li 4, 1
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; P8-NEXT: iseleq 3, 3, 4
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; P8-NEXT: cmplwi 3, 0
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; P8-NEXT: bne 0, .LBB0_2
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; P8-NEXT: b .LBB0_1
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; P8-NEXT: .LBB0_1: # %if.true
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@ -88,11 +84,7 @@ define i32 @test_choice2(fp128 %a, fp128 %b) #0 {
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; P8-NEXT: nop
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; P8-NEXT: # kill: def $r3 killed $r3 killed $x3
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; P8-NEXT: cmpwi 3, 1
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; P8-NEXT: li 4, 0
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; P8-NEXT: li 3, 1
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; P8-NEXT: isellt 3, 3, 4
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; P8-NEXT: cmplwi 3, 0
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; P8-NEXT: bne 0, .LBB1_2
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; P8-NEXT: blt 0, .LBB1_2
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; P8-NEXT: b .LBB1_1
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; P8-NEXT: .LBB1_1: # %if.true
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; P8-NEXT: bl foo
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@ -115,37 +107,30 @@ define i32 @test_choice2(fp128 %a, fp128 %b) #0 {
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; P9: # %bb.0: # %entry
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; P9-NEXT: mflr 0
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; P9-NEXT: std 0, 16(1)
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; P9-NEXT: stdu 1, -128(1)
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; P9-NEXT: xscmpuqp 7, 2, 3
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; P9-NEXT: mfocrf 3, 1
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; P9-NEXT: rotlwi 3, 3, 28
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; P9-NEXT: stw 3, 124(1)
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; P9-NEXT: mfocrf 3, 1
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; P9-NEXT: lwz 4, 124(1)
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; P9-NEXT: rotlwi 4, 4, 4
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; P9-NEXT: mtocrf 1, 4
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; P9-NEXT: clrlwi 3, 3, 31
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; P9-NEXT: xori 4, 3, 1
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; P9-NEXT: mfocrf 3, 1
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; P9-NEXT: rlwinm 3, 3, 30, 31, 31
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; P9-NEXT: xori 3, 3, 1
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; P9-NEXT: and 3, 3, 4
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; P9-NEXT: cmplwi 3, 0
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; P9-NEXT: bne 0, .LBB1_2
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; P9-NEXT: stdu 1, -112(1)
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; P9-NEXT: xscmpuqp 0, 2, 3
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; P9-NEXT: crmove 20, 3
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; P9-NEXT: crnot 21, 20
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; P9-NEXT: crmove 20, 1
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; P9-NEXT: crnot 20, 20
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; P9-NEXT: crand 20, 20, 21
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; P9-NEXT: crxor 21, 21, 21
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; P9-NEXT: crxor 20, 20, 21
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; P9-NEXT: bc 12, 20, .LBB1_2
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; P9-NEXT: b .LBB1_1
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; P9-NEXT: .LBB1_1: # %if.true
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; P9-NEXT: bl foo
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; P9-NEXT: nop
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; P9-NEXT: stw 3, 120(1) # 4-byte Folded Spill
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; P9-NEXT: stw 3, 108(1) # 4-byte Folded Spill
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; P9-NEXT: b .LBB1_3
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; P9-NEXT: .LBB1_2: # %if.false
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; P9-NEXT: bl bar
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; P9-NEXT: nop
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; P9-NEXT: stw 3, 120(1) # 4-byte Folded Spill
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; P9-NEXT: stw 3, 108(1) # 4-byte Folded Spill
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; P9-NEXT: .LBB1_3: # %final
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; P9-NEXT: lwz 3, 120(1) # 4-byte Folded Reload
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; P9-NEXT: lwz 3, 108(1) # 4-byte Folded Reload
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; P9-NEXT: clrldi 3, 3, 32
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; P9-NEXT: addi 1, 1, 128
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; P9-NEXT: addi 1, 1, 112
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; P9-NEXT: ld 0, 16(1)
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; P9-NEXT: mtlr 0
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; P9-NEXT: blr
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@ -175,10 +160,8 @@ define i32 @test_choice3(fp128 %a, fp128 %b) #0 {
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; P8-NEXT: bl __ltkf2
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; P8-NEXT: nop
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; P8-NEXT: # kill: def $r3 killed $r3 killed $x3
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; P8-NEXT: not 3, 3
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; P8-NEXT: srwi 3, 3, 31
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; P8-NEXT: cmplwi 3, 0
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; P8-NEXT: bne 0, .LBB2_2
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; P8-NEXT: cmpwi 3, -1
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; P8-NEXT: bgt 0, .LBB2_2
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; P8-NEXT: b .LBB2_1
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; P8-NEXT: .LBB2_1: # %if.true
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; P8-NEXT: bl foo
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@ -2,7 +2,7 @@
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define i1 @TestULT(double %t0) {
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; CHECK-LABEL: TestULT:
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; CHECK: xscmpudp
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp ult double %t0, 0.000000e+00
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@ -49,7 +49,7 @@ good:
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define i1 @TestUEQ(double %t0) {
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; CHECK-LABEL: TestUEQ:
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; CHECK: xscmpudp
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp ueq double %t0, 0.000000e+00
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@ -64,7 +64,7 @@ good:
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define i1 @TestUGT(double %t0) {
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; CHECK-LABEL: TestUGT:
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; CHECK: xscmpudp
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp ugt double %t0, 0.000000e+00
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@ -111,7 +111,7 @@ good:
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define i1 @TestOLE(double %t0) {
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; CHECK-LABEL: TestOLE:
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; CHECK: xscmpudp
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp ole double %t0, 0.000000e+00
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@ -126,7 +126,7 @@ good:
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define i1 @TestONE(double %t0) {
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; CHECK-LABEL: TestONE:
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; CHECK: xscmpudp
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp one double %t0, 0.000000e+00
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@ -173,7 +173,7 @@ good:
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|
||||
define i1 @TestOGE(double %t0) {
|
||||
; CHECK-LABEL: TestOGE:
|
||||
; CHECK: xscmpudp
|
||||
; CHECK: fcmpu
|
||||
; CHECK: blr
|
||||
entry:
|
||||
%t1 = fcmp oge double %t0, 0.000000e+00
|
||||
|
|
|
|||
|
|
@ -5,25 +5,19 @@
|
|||
define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
|
||||
; CHECK-LABEL: une_ppcf128:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xscmpudp cr7, f1, f3
|
||||
; CHECK-NEXT: mfocrf r3, 1
|
||||
; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
|
||||
; CHECK-NEXT: xscmpudp cr7, f2, f4
|
||||
; CHECK-NEXT: mfocrf r4, 1
|
||||
; CHECK-NEXT: rlwinm r4, r4, 31, 31, 31
|
||||
; CHECK-NEXT: xori r4, r4, 1
|
||||
; CHECK-NEXT: and r4, r3, r4
|
||||
; CHECK-NEXT: xscmpudp cr7, f1, f3
|
||||
; CHECK-NEXT: mfocrf r3, 1
|
||||
; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: xscmpudp cr7, f1, f3
|
||||
; CHECK-NEXT: mfocrf r5, 1
|
||||
; CHECK-NEXT: rlwinm r5, r5, 31, 31, 31
|
||||
; CHECK-NEXT: xori r5, r5, 1
|
||||
; CHECK-NEXT: and r3, r3, r5
|
||||
; CHECK-NEXT: or r3, r3, r4
|
||||
; CHECK-NEXT: # kill: def $r4 killed $r3
|
||||
; CHECK-NEXT: fcmpu cr0, f1, f3
|
||||
; CHECK-NEXT: crmove 4*cr5+lt, eq
|
||||
; CHECK-NEXT: fcmpu cr1, f2, f4
|
||||
; CHECK-NEXT: crmove 4*cr5+gt, 4*cr1+eq
|
||||
; CHECK-NEXT: crnot 4*cr5+gt, 4*cr5+gt
|
||||
; CHECK-NEXT: crand 4*cr5+gt, 4*cr5+lt, 4*cr5+gt
|
||||
; CHECK-NEXT: crmove 4*cr5+lt, eq
|
||||
; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt
|
||||
; CHECK-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+lt
|
||||
; CHECK-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
|
||||
; CHECK-NEXT: li r4, 0
|
||||
; CHECK-NEXT: li r3, 1
|
||||
; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt
|
||||
; CHECK-NEXT: clrldi r3, r3, 32
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
|
|
@ -36,28 +30,19 @@ entry:
|
|||
define i32 @ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
|
||||
; CHECK-LABEL: ogt_ppcf128:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xscmpudp cr7, f1, f3
|
||||
; CHECK-NEXT: mfocrf r3, 1
|
||||
; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
|
||||
; CHECK-NEXT: xscmpudp cr7, f2, f4
|
||||
; CHECK-NEXT: mfocrf r4, 1
|
||||
; CHECK-NEXT: rlwinm r4, r4, 30, 31, 31
|
||||
; CHECK-NEXT: and r4, r3, r4
|
||||
; CHECK-NEXT: xscmpudp cr0, f1, f3
|
||||
; CHECK-NEXT: mfocrf r3, 128
|
||||
; CHECK-NEXT: stw r3, -4(r1)
|
||||
; CHECK-NEXT: xscmpudp cr7, f1, f3
|
||||
; CHECK-NEXT: mfocrf r3, 1
|
||||
; CHECK-NEXT: lwz r5, -4(r1)
|
||||
; CHECK-NEXT: rotlwi r5, r5, 4
|
||||
; CHECK-NEXT: mtocrf 1, r5
|
||||
; CHECK-NEXT: rlwinm r5, r3, 30, 31, 31
|
||||
; CHECK-NEXT: mfocrf r3, 1
|
||||
; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: and r3, r3, r5
|
||||
; CHECK-NEXT: or r3, r3, r4
|
||||
; CHECK-NEXT: # kill: def $r4 killed $r3
|
||||
; CHECK-NEXT: fcmpu cr0, f1, f3
|
||||
; CHECK-NEXT: crmove 4*cr5+lt, eq
|
||||
; CHECK-NEXT: fcmpu cr1, f2, f4
|
||||
; CHECK-NEXT: crmove 4*cr5+gt, 4*cr1+gt
|
||||
; CHECK-NEXT: crand 4*cr5+gt, 4*cr5+lt, 4*cr5+gt
|
||||
; CHECK-NEXT: crmove 4*cr5+lt, eq
|
||||
; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt
|
||||
; CHECK-NEXT: crmove 4*cr5+eq, gt
|
||||
; CHECK-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+eq
|
||||
; CHECK-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
|
||||
; CHECK-NEXT: li r4, 0
|
||||
; CHECK-NEXT: li r3, 1
|
||||
; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt
|
||||
; CHECK-NEXT: clrldi r3, r3, 32
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
|
|
@ -69,12 +54,14 @@ entry:
|
|||
define i1 @test_f128(fp128 %a, fp128 %b) #0 {
|
||||
; CHECK-LABEL: test_f128:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xscmpuqp cr7, v2, v3
|
||||
; CHECK-NEXT: mfocrf r3, 1
|
||||
; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
|
||||
; CHECK-NEXT: xori r4, r3, 1
|
||||
; CHECK-NEXT: # implicit-def: $x3
|
||||
; CHECK-NEXT: mr r3, r4
|
||||
; CHECK-NEXT: xscmpuqp cr0, v2, v3
|
||||
; CHECK-NEXT: crmove 4*cr5+lt, eq
|
||||
; CHECK-NEXT: xscmpuqp cr0, v2, v3
|
||||
; CHECK-NEXT: crmove 4*cr5+gt, eq
|
||||
; CHECK-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
|
||||
; CHECK-NEXT: li r4, 0
|
||||
; CHECK-NEXT: li r3, 1
|
||||
; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%0 = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
|
||||
|
|
@ -84,11 +71,9 @@ entry:
|
|||
define i1 @testbr_f64(double %a, double %b) #0 {
|
||||
; CHECK-LABEL: testbr_f64:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xscmpudp cr7, f1, f2
|
||||
; CHECK-NEXT: mfocrf r3, 1
|
||||
; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
|
||||
; CHECK-NEXT: cmplwi r3, 0
|
||||
; CHECK-NEXT: bne cr0, .LBB3_2
|
||||
; CHECK-NEXT: fcmpu cr0, f1, f2
|
||||
; CHECK-NEXT: crmove 4*cr5+lt, eq
|
||||
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB3_2
|
||||
; CHECK-NEXT: b .LBB3_1
|
||||
; CHECK-NEXT: .LBB3_1: # %tr
|
||||
; CHECK-NEXT: li r3, -1
|
||||
|
|
@ -108,11 +93,9 @@ fl:
|
|||
define i1 @testbr_f32(float %a, float %b) #0 {
|
||||
; CHECK-LABEL: testbr_f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fcmpu cr7, f1, f2
|
||||
; CHECK-NEXT: mfocrf r3, 1
|
||||
; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
|
||||
; CHECK-NEXT: cmplwi r3, 0
|
||||
; CHECK-NEXT: bne cr0, .LBB4_2
|
||||
; CHECK-NEXT: fcmpu cr0, f1, f2
|
||||
; CHECK-NEXT: crmove 4*cr5+lt, eq
|
||||
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB4_2
|
||||
; CHECK-NEXT: b .LBB4_1
|
||||
; CHECK-NEXT: .LBB4_1: # %tr
|
||||
; CHECK-NEXT: li r3, -1
|
||||
|
|
|
|||
|
|
@ -7,11 +7,11 @@ define i1 @Test(double %a) {
|
|||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xscvdpsxws 0, 1
|
||||
; CHECK-NEXT: mffprwz 3, 0
|
||||
; CHECK-NEXT: xori 3, 3, 65534
|
||||
; CHECK-NEXT: cntlzw 3, 3
|
||||
; CHECK-NEXT: srwi 4, 3, 5
|
||||
; CHECK-NEXT: # implicit-def: $x3
|
||||
; CHECK-NEXT: mr 3, 4
|
||||
; CHECK-NEXT: cmplwi 3, 65534
|
||||
; CHECK-NEXT: crmove 20, 2
|
||||
; CHECK-NEXT: li 4, 0
|
||||
; CHECK-NEXT: li 3, 1
|
||||
; CHECK-NEXT: isel 3, 3, 4, 20
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%conv = fptoui double %a to i16
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@ define void @i32_ZextLoad_i1() {
|
|||
; CHECK-LE-LABEL: i32_ZextLoad_i1:
|
||||
; CHECK-LE: # %bb.0: # %entry
|
||||
; CHECK-LE-NEXT: plbz r3, GlobLd1@PCREL(0), 1
|
||||
; CHECK-LE-NEXT: clrldi r3, r3, 63
|
||||
; CHECK-LE-NEXT: pstb r3, GlobSt1@PCREL(0), 1
|
||||
; CHECK-LE-NEXT: blr
|
||||
;
|
||||
|
|
@ -53,6 +54,7 @@ define void @i32_ZextLoad_i1() {
|
|||
; CHECK-BE-NEXT: addis r3, r2, GlobLd1@toc@ha
|
||||
; CHECK-BE-NEXT: addis r4, r2, GlobSt1@toc@ha
|
||||
; CHECK-BE-NEXT: lbz r3, GlobLd1@toc@l(r3)
|
||||
; CHECK-BE-NEXT: clrldi r3, r3, 63
|
||||
; CHECK-BE-NEXT: stb r3, GlobSt1@toc@l(r4)
|
||||
; CHECK-BE-NEXT: blr
|
||||
entry:
|
||||
|
|
@ -77,11 +79,11 @@ define dso_local i1 @i32_ExtLoad_i1() local_unnamed_addr #0 {
|
|||
; CHECK-LE-NEXT: paddi r3, 0, Glob1@PCREL, 1
|
||||
; CHECK-LE-NEXT: paddi r4, 0, Glob2@PCREL, 1
|
||||
; CHECK-LE-NEXT: bl Decl@notoc
|
||||
; CHECK-LE-NEXT: plbz r4, GlobLd1@PCREL(0), 1
|
||||
; CHECK-LE-NEXT: cmplwi r3, 0
|
||||
; CHECK-LE-NEXT: li r3, 1
|
||||
; CHECK-LE-NEXT: iseleq r3, 0, r3
|
||||
; CHECK-LE-NEXT: and r3, r3, r4
|
||||
; CHECK-LE-NEXT: cmpwi cr1, r3, 0
|
||||
; CHECK-LE-NEXT: plbz r3, GlobLd1@PCREL(0), 1
|
||||
; CHECK-LE-NEXT: andi. r3, r3, 1
|
||||
; CHECK-LE-NEXT: crandc 4*cr5+lt, gt, 4*cr1+eq
|
||||
; CHECK-LE-NEXT: setbc r3, 4*cr5+lt
|
||||
; CHECK-LE-NEXT: addi r1, r1, 32
|
||||
; CHECK-LE-NEXT: ld r0, 16(r1)
|
||||
; CHECK-LE-NEXT: mtlr r0
|
||||
|
|
@ -100,12 +102,12 @@ define dso_local i1 @i32_ExtLoad_i1() local_unnamed_addr #0 {
|
|||
; CHECK-BE-NEXT: addi r4, r4, Glob2@toc@l
|
||||
; CHECK-BE-NEXT: bl Decl
|
||||
; CHECK-BE-NEXT: nop
|
||||
; CHECK-BE-NEXT: addis r4, r2, GlobLd1@toc@ha
|
||||
; CHECK-BE-NEXT: cmplwi r3, 0
|
||||
; CHECK-BE-NEXT: li r3, 1
|
||||
; CHECK-BE-NEXT: lbz r4, GlobLd1@toc@l(r4)
|
||||
; CHECK-BE-NEXT: iseleq r3, 0, r3
|
||||
; CHECK-BE-NEXT: and r3, r3, r4
|
||||
; CHECK-BE-NEXT: cmpwi cr1, r3, 0
|
||||
; CHECK-BE-NEXT: addis r3, r2, GlobLd1@toc@ha
|
||||
; CHECK-BE-NEXT: lbz r3, GlobLd1@toc@l(r3)
|
||||
; CHECK-BE-NEXT: andi. r3, r3, 1
|
||||
; CHECK-BE-NEXT: crandc 4*cr5+lt, gt, 4*cr1+eq
|
||||
; CHECK-BE-NEXT: setbc r3, 4*cr5+lt
|
||||
; CHECK-BE-NEXT: addi r1, r1, 112
|
||||
; CHECK-BE-NEXT: ld r0, 16(r1)
|
||||
; CHECK-BE-NEXT: mtlr r0
|
||||
|
|
|
|||
Loading…
Reference in New Issue