forked from OSchip/llvm-project
AMDGPU: Fold fneg into fadd
Patch mostly by Fiona Glaser llvm-svn: 291731
This commit is contained in:
Matt Arsenault
parent
f91e47374c
commit
2529fba989
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@ -477,6 +477,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::FADD);
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setTargetDAGCombine(ISD::FSUB);
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setTargetDAGCombine(ISD::FNEG);
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}
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//===----------------------------------------------------------------------===//
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@ -2805,6 +2806,63 @@ SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
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return performCtlzCombine(SDLoc(N), Cond, True, False, DCI);
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}
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static bool fnegFoldsIntoOp(unsigned Opc) {
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switch (Opc) {
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FMA:
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case ISD::FMAD:
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return true;
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default:
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return false;
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}
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}
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SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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unsigned Opc = N0.getOpcode();
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// If the input has multiple uses and we can either fold the negate down, or
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// the other uses cannot, give up. This both prevents unprofitable
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// transformations and infinite loops: we won't repeatedly try to fold around
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// a negate that has no 'good' form.
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//
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// TODO: Check users can fold
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if (fnegFoldsIntoOp(Opc) && !N0.hasOneUse())
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return SDValue();
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SDLoc SL(N);
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switch (Opc) {
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case ISD::FADD: {
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// (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
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SDValue LHS = N0.getOperand(0);
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SDValue RHS = N0.getOperand(1);
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if (LHS.getOpcode() != ISD::FNEG)
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LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
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else
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LHS = LHS.getOperand(0);
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if (RHS.getOpcode() != ISD::FNEG)
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RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
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else
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RHS = RHS.getOperand(0);
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SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS);
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if (!N0.hasOneUse())
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DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
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return Res;
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}
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default:
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return SDValue();
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}
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}
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SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -2910,6 +2968,8 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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return performMulLoHi24Combine(N, DCI);
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case ISD::SELECT:
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return performSelectCombine(N, DCI);
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case ISD::FNEG:
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return performFNegCombine(N, DCI);
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case AMDGPUISD::BFE_I32:
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case AMDGPUISD::BFE_U32: {
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assert(!N->getValueType(0).isVector() &&
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@ -84,6 +84,7 @@ protected:
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SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
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SDValue RHS, DAGCombinerInfo &DCI) const;
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SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
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@ -0,0 +1,179 @@
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; GCN-LABEL: {{^}}v_fneg_add_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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; GCN: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[A]], [[B]]
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; GCN-NEXT: buffer_store_dword [[RESULT]]
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define void @v_fneg_add_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%b = load volatile float, float addrspace(1)* %b.gep
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%add = fadd float %a, %b
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%fneg = fsub float -0.000000e+00, %add
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store float %fneg, float addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_add_store_use_add_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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; GCN-DAG: v_add_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
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; GCN-DAG: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], 0x80000000, [[ADD]]
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; GCN-NEXT: buffer_store_dword [[NEG_ADD]]
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; GCN-NEXT: buffer_store_dword [[ADD]]
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define void @v_fneg_add_store_use_add_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%b = load volatile float, float addrspace(1)* %b.gep
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%add = fadd float %a, %b
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%fneg = fsub float -0.000000e+00, %add
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store volatile float %fneg, float addrspace(1)* %out
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store volatile float %add, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_add_multi_use_add_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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; GCN-DAG: v_add_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
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; GCN-DAG: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], 0x80000000, [[ADD]]
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; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], 4.0, [[ADD]]
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; GCN-NEXT: buffer_store_dword [[NEG_ADD]]
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; GCN-NEXT: buffer_store_dword [[MUL]]
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define void @v_fneg_add_multi_use_add_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%b = load volatile float, float addrspace(1)* %b.gep
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%add = fadd float %a, %b
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%fneg = fsub float -0.000000e+00, %add
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%use1 = fmul float %add, 4.0
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store volatile float %fneg, float addrspace(1)* %out
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store volatile float %use1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_add_fneg_x_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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; GCN: v_subrev_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
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; GCN-NEXT: buffer_store_dword [[ADD]]
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define void @v_fneg_add_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%b = load volatile float, float addrspace(1)* %b.gep
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%fneg.a = fsub float -0.000000e+00, %a
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%add = fadd float %fneg.a, %b
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%fneg = fsub float -0.000000e+00, %add
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store volatile float %fneg, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_add_x_fneg_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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; GCN: v_subrev_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
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; GCN-NEXT: buffer_store_dword [[ADD]]
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define void @v_fneg_add_x_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%b = load volatile float, float addrspace(1)* %b.gep
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%fneg.b = fsub float -0.000000e+00, %b
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%add = fadd float %a, %fneg.b
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%fneg = fsub float -0.000000e+00, %add
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store volatile float %fneg, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_add_fneg_fneg_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
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; GCN-NEXT: buffer_store_dword [[ADD]]
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define void @v_fneg_add_fneg_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%b = load volatile float, float addrspace(1)* %b.gep
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%fneg.a = fsub float -0.000000e+00, %a
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%fneg.b = fsub float -0.000000e+00, %b
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%add = fadd float %fneg.a, %fneg.b
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%fneg = fsub float -0.000000e+00, %add
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store volatile float %fneg, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_add_store_use_fneg_x_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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; GCN-DAG: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
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; GCN-DAG: v_subrev_f32_e32 [[NEG_ADD:v[0-9]+]], [[B]], [[A]]
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; GCN-NEXT: buffer_store_dword [[NEG_ADD]]
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; GCN-NEXT: buffer_store_dword [[NEG_A]]
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define void @v_fneg_add_store_use_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%b = load volatile float, float addrspace(1)* %b.gep
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%fneg.a = fsub float -0.000000e+00, %a
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%add = fadd float %fneg.a, %b
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%fneg = fsub float -0.000000e+00, %add
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store volatile float %fneg, float addrspace(1)* %out
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store volatile float %fneg.a, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_add_multi_use_fneg_x_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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; GCN-DAG: v_subrev_f32_e32 [[NEG_ADD:v[0-9]+]], [[B]], [[A]]
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; GCN-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
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; GCN-NEXT: buffer_store_dword [[NEG_ADD]]
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; GCN-NEXT: buffer_store_dword [[MUL]]
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define void @v_fneg_add_multi_use_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float %c) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%b = load volatile float, float addrspace(1)* %b.gep
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%fneg.a = fsub float -0.000000e+00, %a
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%add = fadd float %fneg.a, %b
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%fneg = fsub float -0.000000e+00, %add
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%use1 = fmul float %fneg.a, %c
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store volatile float %fneg, float addrspace(1)* %out
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store volatile float %use1, float addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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