forked from OSchip/llvm-project
Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code. llvm-svn: 49666
This commit is contained in:
parent
d80edddccd
commit
2505d86783
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@ -326,17 +326,17 @@ public:
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SDOperand getMemcpy(SDOperand Chain, SDOperand Dst, SDOperand Src,
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SDOperand Size, unsigned Align,
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bool AlwaysInline,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff);
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff);
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SDOperand getMemmove(SDOperand Chain, SDOperand Dst, SDOperand Src,
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SDOperand Size, unsigned Align,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff);
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff);
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SDOperand getMemset(SDOperand Chain, SDOperand Dst, SDOperand Src,
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SDOperand Size, unsigned Align,
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Value *DstSV, uint64_t DstOff);
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const Value *DstSV, uint64_t DstOff);
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/// getSetCC - Helper function to make it easier to build SetCC's if you just
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/// have an ISD::CondCode instead of an SDOperand.
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@ -967,8 +967,8 @@ public:
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SDOperand Op1, SDOperand Op2,
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SDOperand Op3, unsigned Align,
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bool AlwaysInline,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff) {
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff) {
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return SDOperand();
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}
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@ -983,8 +983,8 @@ public:
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SDOperand Chain,
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SDOperand Op1, SDOperand Op2,
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SDOperand Op3, unsigned Align,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff) {
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff) {
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return SDOperand();
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}
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@ -999,7 +999,7 @@ public:
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SDOperand Chain,
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SDOperand Op1, SDOperand Op2,
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SDOperand Op3, unsigned Align,
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Value *DstSV, uint64_t DstOff) {
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const Value *DstSV, uint64_t DstOff) {
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return SDOperand();
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}
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@ -2500,8 +2500,8 @@ static SDOperand getMemcpyLoadsAndStores(SelectionDAG &DAG,
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SDOperand Src, uint64_t Size,
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unsigned Align,
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bool AlwaysInline,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff) {
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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// Expand memcpy to a series of store ops if the size operand falls below
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@ -2573,7 +2573,7 @@ static SDOperand getMemsetStores(SelectionDAG &DAG,
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SDOperand Chain, SDOperand Dst,
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SDOperand Src, uint64_t Size,
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unsigned Align,
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Value *DstSV, uint64_t DstOff) {
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const Value *DstSV, uint64_t DstOff) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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// Expand memset to a series of load/store ops if the size operand
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@ -2604,8 +2604,8 @@ static SDOperand getMemsetStores(SelectionDAG &DAG,
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SDOperand SelectionDAG::getMemcpy(SDOperand Chain, SDOperand Dst,
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SDOperand Src, SDOperand Size,
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unsigned Align, bool AlwaysInline,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff) {
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff) {
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// Check to see if we should lower the memcpy to loads and stores first.
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// For cases within the target-specified limits, this is the best choice.
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@ -2658,8 +2658,8 @@ SDOperand SelectionDAG::getMemcpy(SDOperand Chain, SDOperand Dst,
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SDOperand SelectionDAG::getMemmove(SDOperand Chain, SDOperand Dst,
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SDOperand Src, SDOperand Size,
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unsigned Align,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff) {
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff) {
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// TODO: Optimize small memmove cases with simple loads and stores,
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// ensuring that all loads precede all stores. This can cause severe
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@ -2691,7 +2691,7 @@ SDOperand SelectionDAG::getMemmove(SDOperand Chain, SDOperand Dst,
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SDOperand SelectionDAG::getMemset(SDOperand Chain, SDOperand Dst,
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SDOperand Src, SDOperand Size,
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unsigned Align,
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Value *DstSV, uint64_t DstOff) {
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const Value *DstSV, uint64_t DstOff) {
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// Check to see if we should lower the memset to stores first.
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// For cases within the target-specified limits, this is the best choice.
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@ -1247,8 +1247,8 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
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SDOperand Dst, SDOperand Src,
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SDOperand Size, unsigned Align,
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bool AlwaysInline,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff){
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff){
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// Do repeated 4-byte loads and stores. To be improved.
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// This requires 4-byte alignment.
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if ((Align & 3) != 0)
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@ -149,8 +149,8 @@ namespace llvm {
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SDOperand Dst, SDOperand Src,
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SDOperand Size, unsigned Align,
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bool AlwaysInline,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff);
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff);
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};
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}
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@ -4664,7 +4664,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
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SDOperand Chain,
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SDOperand Dst, SDOperand Src,
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SDOperand Size, unsigned Align,
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Value *DstSV, uint64_t DstOff) {
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const Value *DstSV, uint64_t DstOff) {
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ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
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/// If not DWORD aligned or size is more than the threshold, call the library.
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@ -4804,8 +4804,8 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
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SDOperand Dst, SDOperand Src,
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SDOperand Size, unsigned Align,
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bool AlwaysInline,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff){
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff){
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// This requires the copy size to be a constant, preferrably
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// within a subtarget-specific limit.
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@ -550,14 +550,14 @@ namespace llvm {
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SDOperand Chain,
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SDOperand Dst, SDOperand Src,
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SDOperand Size, unsigned Align,
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Value *DstSV, uint64_t DstOff);
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const Value *DstSV, uint64_t DstOff);
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SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG,
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SDOperand Chain,
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SDOperand Dst, SDOperand Src,
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SDOperand Size, unsigned Align,
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bool AlwaysInline,
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Value *DstSV, uint64_t DstOff,
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Value *SrcSV, uint64_t SrcOff);
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const Value *DstSV, uint64_t DstOff,
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const Value *SrcSV, uint64_t SrcOff);
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};
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}
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