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ARM VREV64df and VREV64qf can just be patterns. The instruction is the same 

as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485
This commit is contained in:
Jim Grosbach 2011-03-11 20:18:05 +00:00
parent b7cfba4cb1
commit 24fe5e36ea
2 changed files with 2 additions and 9 deletions
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4
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -4591,12 +4591,12 @@ class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
// VREV32 : Vector Reverse elements within 32-bit words

7
llvm/utils/TableGen/ARMDecoderEmitter.cpp
View File

@ -1654,13 +1654,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
Name == "VEXTq16" || Name == "VEXTq32" || Name == "VEXTqf")
return false;
// Vector Reverse is similar to Vector Extract. There is no distinction
// between data types, other than size.
//
// VREV64df is equivalent to VREV64d32.
// VREV64qf is equivalent to VREV64q32.
if (Name == "VREV64df" || Name == "VREV64qf") return false;
// VDUPLNfd is equivalent to VDUPLN32d.
// VDUPLNfq is equivalent to VDUPLN32q.
// VLD1df is equivalent to VLD1d32.