forked from OSchip/llvm-project
parent
2471f6ce0f
commit
24e8f0cfe6
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@ -146,8 +146,8 @@ unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
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unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass* RC) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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@ -159,8 +159,8 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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MI->addOperand(MachineOperand::CreateReg(Op0, false));
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@ -173,8 +173,8 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, unsigned Op1) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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MI->addOperand(MachineOperand::CreateReg(Op0, false));
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