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[mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves 

Summary:
This is similar to r210771 which did the same thing for MTHC1.

Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the
wrong definitions.

Differential Revision: http://reviews.llvm.org/D4483

llvm-svn: 212936
This commit is contained in:
Daniel Sanders 2014-07-14 12:41:31 +00:00
parent 3064620d0d
commit 24e08fd5c0
6 changed files with 182 additions and 186 deletions
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17
llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -142,11 +142,6 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
@ -914,18 +909,6 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,

12
llvm/lib/Target/Mips/MipsInstrFPU.td
View File

@ -362,11 +362,15 @@ def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
bitconvert>, MFC1_FM<0>; bitconvert>, MFC1_FM<0>;
def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
bitconvert>, MFC1_FM<4>; bitconvert>, MFC1_FM<4>;
def MFHC1 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>, def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM<3>, ISA_MIPS32R2; MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
let DecoderNamespace = "Mips64";
}
def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
def MTHC1_D64 : MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
let DecoderNamespace = "Mips64"; let DecoderNamespace = "Mips64";
} }

9
llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
View File

@ -521,8 +521,9 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
if (SubIdx == Mips::sub_hi && FP64) { if (SubIdx == Mips::sub_hi && TM.getSubtarget<MipsSubtarget>().hasMTHC1()) {
// FIXME: The .addReg(SrcReg, RegState::Implicit) is a white lie used to // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
// claim to read the whole 64-bits as part of a white lie used to
// temporarily work around a widespread bug in the -mfp64 support. // temporarily work around a widespread bug in the -mfp64 support.
// The problem is that none of the 32-bit fpu ops mention the fact // The problem is that none of the 32-bit fpu ops mention the fact
// that they clobber the upper 32-bits of the 64-bit FPR. Fixing that // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
@ -533,8 +534,8 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
// We therefore pretend that it reads the bottom 32-bits to // We therefore pretend that it reads the bottom 32-bits to
// artificially create a dependency and prevent the scheduler // artificially create a dependency and prevent the scheduler
// changing the behaviour of the code. // changing the behaviour of the code.
BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg( BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
SrcReg, RegState::Implicit); .addReg(SrcReg);
} else } else
BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
} }

34
llvm/test/CodeGen/Mips/buildpairextractelementf64.ll
View File

@ -1,15 +1,19 @@
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=FP32 -check-prefix=CHECK ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL
; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=FP32 -check-prefix=CHECK ; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
@a = external global i32 @a = external global i32
; CHECK-LABEL: f: ; ALL-LABEL: f:
; FP32: mtc1
; FP32: mtc1 ; NO-MFHC1: mtc1
; FP64-DAG: mtc1 ; NO-MFHC1: mtc1
; FP64-DAG: mthc1
; HAS-MFHC1-DAG: mtc1
; HAS-MFHC1-DAG: mthc1
define double @f(i32 %a1, double %d) nounwind { define double @f(i32 %a1, double %d) nounwind {
entry: entry:
@ -18,11 +22,13 @@ entry:
ret double %add ret double %add
} }
; CHECK-LABEL: f3: ; ALL-LABEL: f3:
; FP32: mfc1
; FP32: mfc1 ; NO-MFHC1: mfc1
; FP64-DAG: mfc1 ; NO-MFHC1: mfc1
; FP64-DAG: mfhc1
; HAS-MFHC1-DAG: mfc1
; HAS-MFHC1-DAG: mfhc1
define void @f3(double %d, i32 %a1) nounwind { define void @f3(double %d, i32 %a1) nounwind {
entry: entry:

8
llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
View File

@ -123,7 +123,7 @@ entry:
; 32R1-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}}) ; 32R1-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
; 32R2-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 ; 32R2-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; 32R2-LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13 ; 32R2-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
; 32R2-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}}) ; 32R2-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
; 32R2-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}}) ; 32R2-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
@ -140,7 +140,7 @@ entry:
; 32R1-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]]) ; 32R1-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
; 32R2-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 ; 32R2-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; 32R2-LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13 ; 32R2-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
; 32R2-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0) ; 32R2-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
; 32R2-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]]) ; 32R2-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
; 32R2-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0) ; 32R2-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
@ -159,7 +159,7 @@ entry:
; 32R1-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}}) ; 32R1-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
; 32R2-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 ; 32R2-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; 32R2-BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13 ; 32R2-BE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
; 32R2-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}}) ; 32R2-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
; 32R2-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}}) ; 32R2-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
@ -225,7 +225,7 @@ entry:
; 32R1-DAG: sw $[[R1]], 4(${{[0-9]+}}) ; 32R1-DAG: sw $[[R1]], 4(${{[0-9]+}})
; 32R2-DAG: mfc1 $[[R0:[0-9]+]], $f12 ; 32R2-DAG: mfc1 $[[R0:[0-9]+]], $f12
; 32R2-DAG: mfc1 $[[R1:[0-9]+]], $f13 ; 32R2-DAG: mfhc1 $[[R1:[0-9]+]], $f12
; 32R2-DAG: sw $[[R0]], 0(${{[0-9]+}}) ; 32R2-DAG: sw $[[R0]], 0(${{[0-9]+}})
; 32R2-DAG: sw $[[R1]], 4(${{[0-9]+}}) ; 32R2-DAG: sw $[[R1]], 4(${{[0-9]+}})

288
llvm/test/CodeGen/Mips/o32_cc.ll
View File

@ -1,12 +1,13 @@
; RUN: llc -march=mipsel < %s | FileCheck %s ; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=ALL %s
; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s ; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck -check-prefix=ALL %s
; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=FP32EL %s ; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=NO-MFHC1 %s
; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck -check-prefix=FP64EL %s ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-MFHC1 %s
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-MFHC1 %s
; $f12, $f14 ; $f12, $f14
; CHECK-LABEL: testlowercall0: ; ALL-LABEL: testlowercall0:
; CHECK-DAG: ldc1 $f12, %lo ; ALL-DAG: ldc1 $f12, %lo
; CHECK-DAG: ldc1 $f14, %lo ; ALL-DAG: ldc1 $f14, %lo
define void @testlowercall0() nounwind { define void @testlowercall0() nounwind {
entry: entry:
tail call void @f0(double 5.000000e+00, double 6.000000e+00) nounwind tail call void @f0(double 5.000000e+00, double 6.000000e+00) nounwind
@ -16,9 +17,9 @@ entry:
declare void @f0(double, double) declare void @f0(double, double)
; $f12, $f14 ; $f12, $f14
; CHECK-LABEL: testlowercall1: ; ALL-LABEL: testlowercall1:
; CHECK-DAG: lwc1 $f12, %lo ; ALL-DAG: lwc1 $f12, %lo
; CHECK-DAG: lwc1 $f14, %lo ; ALL-DAG: lwc1 $f14, %lo
define void @testlowercall1() nounwind { define void @testlowercall1() nounwind {
entry: entry:
tail call void @f1(float 8.000000e+00, float 9.000000e+00) nounwind tail call void @f1(float 8.000000e+00, float 9.000000e+00) nounwind
@ -28,9 +29,9 @@ entry:
declare void @f1(float, float) declare void @f1(float, float)
; $f12, $f14 ; $f12, $f14
; CHECK-LABEL: testlowercall2: ; ALL-LABEL: testlowercall2:
; CHECK-DAG: lwc1 $f12, %lo ; ALL-DAG: lwc1 $f12, %lo
; CHECK-DAG: ldc1 $f14, %lo ; ALL-DAG: ldc1 $f14, %lo
define void @testlowercall2() nounwind { define void @testlowercall2() nounwind {
entry: entry:
tail call void @f2(float 8.000000e+00, double 6.000000e+00) nounwind tail call void @f2(float 8.000000e+00, double 6.000000e+00) nounwind
@ -40,9 +41,9 @@ entry:
declare void @f2(float, double) declare void @f2(float, double)
; $f12, $f14 ; $f12, $f14
; CHECK-LABEL: testlowercall3: ; ALL-LABEL: testlowercall3:
; CHECK-DAG: ldc1 $f12, %lo ; ALL-DAG: ldc1 $f12, %lo
; CHECK-DAG: lwc1 $f14, %lo ; ALL-DAG: lwc1 $f14, %lo
define void @testlowercall3() nounwind { define void @testlowercall3() nounwind {
entry: entry:
tail call void @f3(double 5.000000e+00, float 9.000000e+00) nounwind tail call void @f3(double 5.000000e+00, float 9.000000e+00) nounwind
@ -52,11 +53,11 @@ entry:
declare void @f3(double, float) declare void @f3(double, float)
; $4, $5, $6, $7 ; $4, $5, $6, $7
; CHECK-LABEL: testlowercall4: ; ALL-LABEL: testlowercall4:
; CHECK-DAG: addiu $4, $zero, 12 ; ALL-DAG: addiu $4, $zero, 12
; CHECK-DAG: addiu $5, $zero, 13 ; ALL-DAG: addiu $5, $zero, 13
; CHECK-DAG: addiu $6, $zero, 14 ; ALL-DAG: addiu $6, $zero, 14
; CHECK-DAG: addiu $7, $zero, 15 ; ALL-DAG: addiu $7, $zero, 15
define void @testlowercall4() nounwind { define void @testlowercall4() nounwind {
entry: entry:
tail call void @f4(i32 12, i32 13, i32 14, i32 15) nounwind tail call void @f4(i32 12, i32 13, i32 14, i32 15) nounwind
@ -66,11 +67,11 @@ entry:
declare void @f4(i32, i32, i32, i32) declare void @f4(i32, i32, i32, i32)
; $f12, $6, stack ; $f12, $6, stack
; CHECK-LABEL: testlowercall5: ; ALL-LABEL: testlowercall5:
; CHECK-DAG: ldc1 $f12, %lo ; ALL-DAG: ldc1 $f12, %lo
; CHECK-DAG: addiu $6, $zero, 23 ; ALL-DAG: addiu $6, $zero, 23
; CHECK-DAG: sw ${{[a-z0-9]+}}, 16($sp) ; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
; CHECK-DAG: sw ${{[a-z0-9]+}}, 20($sp) ; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
define void @testlowercall5() nounwind { define void @testlowercall5() nounwind {
entry: entry:
tail call void @f5(double 1.500000e+01, i32 23, double 1.700000e+01) nounwind tail call void @f5(double 1.500000e+01, i32 23, double 1.700000e+01) nounwind
@ -80,10 +81,10 @@ entry:
declare void @f5(double, i32, double) declare void @f5(double, i32, double)
; $f12, $6, $7 ; $f12, $6, $7
; CHECK-LABEL: testlowercall6: ; ALL-LABEL: testlowercall6:
; CHECK-DAG: ldc1 $f12, %lo ; ALL-DAG: ldc1 $f12, %lo
; CHECK-DAG: addiu $6, $zero, 33 ; ALL-DAG: addiu $6, $zero, 33
; CHECK-DAG: addiu $7, $zero, 24 ; ALL-DAG: addiu $7, $zero, 24
define void @testlowercall6() nounwind { define void @testlowercall6() nounwind {
entry: entry:
tail call void @f6(double 2.500000e+01, i32 33, i32 24) nounwind tail call void @f6(double 2.500000e+01, i32 33, i32 24) nounwind
@ -93,10 +94,10 @@ entry:
declare void @f6(double, i32, i32) declare void @f6(double, i32, i32)
; $f12, $5, $6 ; $f12, $5, $6
; CHECK-LABEL: testlowercall7: ; ALL-LABEL: testlowercall7:
; CHECK-DAG: lwc1 $f12, %lo ; ALL-DAG: lwc1 $f12, %lo
; CHECK-DAG: addiu $5, $zero, 43 ; ALL-DAG: addiu $5, $zero, 43
; CHECK-DAG: addiu $6, $zero, 34 ; ALL-DAG: addiu $6, $zero, 34
define void @testlowercall7() nounwind { define void @testlowercall7() nounwind {
entry: entry:
tail call void @f7(float 1.800000e+01, i32 43, i32 34) nounwind tail call void @f7(float 1.800000e+01, i32 43, i32 34) nounwind
@ -106,12 +107,12 @@ entry:
declare void @f7(float, i32, i32) declare void @f7(float, i32, i32)
; $4, $5, $6, stack ; $4, $5, $6, stack
; CHECK-LABEL: testlowercall8: ; ALL-LABEL: testlowercall8:
; CHECK-DAG: addiu $4, $zero, 22 ; ALL-DAG: addiu $4, $zero, 22
; CHECK-DAG: addiu $5, $zero, 53 ; ALL-DAG: addiu $5, $zero, 53
; CHECK-DAG: addiu $6, $zero, 44 ; ALL-DAG: addiu $6, $zero, 44
; CHECK-DAG: sw ${{[a-z0-9]+}}, 16($sp) ; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
; CHECK-DAG: sw ${{[a-z0-9]+}}, 20($sp) ; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
define void @testlowercall8() nounwind { define void @testlowercall8() nounwind {
entry: entry:
tail call void @f8(i32 22, i32 53, i32 44, double 4.000000e+00) nounwind tail call void @f8(i32 22, i32 53, i32 44, double 4.000000e+00) nounwind
@ -121,11 +122,11 @@ entry:
declare void @f8(i32, i32, i32, double) declare void @f8(i32, i32, i32, double)
; $4, $5, $6, $7 ; $4, $5, $6, $7
; CHECK-LABEL: testlowercall9: ; ALL-LABEL: testlowercall9:
; CHECK-DAG: addiu $4, $zero, 32 ; ALL-DAG: addiu $4, $zero, 32
; CHECK-DAG: addiu $5, $zero, 63 ; ALL-DAG: addiu $5, $zero, 63
; CHECK-DAG: addiu $6, $zero, 54 ; ALL-DAG: addiu $6, $zero, 54
; CHECK-DAG: lui $7, 16688 ; ALL-DAG: lui $7, 16688
define void @testlowercall9() nounwind { define void @testlowercall9() nounwind {
entry: entry:
tail call void @f9(i32 32, i32 63, i32 54, float 1.100000e+01) nounwind tail call void @f9(i32 32, i32 63, i32 54, float 1.100000e+01) nounwind
@ -135,15 +136,16 @@ entry:
declare void @f9(i32, i32, i32, float) declare void @f9(i32, i32, i32, float)
; $4, $5, ($6, $7) ; $4, $5, ($6, $7)
; CHECK-LABEL: testlowercall10: ; ALL-LABEL: testlowercall10:
; CHECK-DAG: addiu $4, $zero, 42
; CHECK-DAG: addiu $5, $zero, 73 ; ALL-DAG: addiu $4, $zero, 42
; FP32EL-LABEL: testlowercall10: ; ALL-DAG: addiu $5, $zero, 73
; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}}
; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}} ; NO-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
; FP64EL-LABEL: testlowercall10: ; NO-MFHC1-DAG: mfc1 $7, $f{{[0-9]+}}
; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}}
; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}} ; HAS-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
; HAS-MFHC1-DAG: mfhc1 $7, $f{{[0-9]+}}
define void @testlowercall10() nounwind { define void @testlowercall10() nounwind {
entry: entry:
tail call void @f10(i32 42, i32 73, double 2.700000e+01) nounwind tail call void @f10(i32 42, i32 73, double 2.700000e+01) nounwind
@ -153,14 +155,14 @@ entry:
declare void @f10(i32, i32, double) declare void @f10(i32, i32, double)
; $4, ($6, $7) ; $4, ($6, $7)
; CHECK-LABEL: testlowercall11: ; ALL-LABEL: testlowercall11:
; CHECK-DAG: addiu $4, $zero, 52 ; ALL-DAG: addiu $4, $zero, 52
; FP32EL-LABEL: testlowercall11:
; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}} ; NO-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}} ; NO-MFHC1-DAG: mfc1 $7, $f{{[0-9]+}}
; FP64EL-LABEL: testlowercall11:
; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}} ; HAS-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}} ; HAS-MFHC1-DAG: mfhc1 $7, $f{{[0-9]+}}
define void @testlowercall11() nounwind { define void @testlowercall11() nounwind {
entry: entry:
tail call void @f11(i32 52, double 1.600000e+01) nounwind tail call void @f11(i32 52, double 1.600000e+01) nounwind
@ -170,11 +172,11 @@ entry:
declare void @f11(i32, double) declare void @f11(i32, double)
; $f12, $f14, $6, $7 ; $f12, $f14, $6, $7
; CHECK-LABEL: testlowercall12: ; ALL-LABEL: testlowercall12:
; CHECK-DAG: lwc1 $f12, %lo ; ALL-DAG: lwc1 $f12, %lo
; CHECK-DAG: lwc1 $f14, %lo ; ALL-DAG: lwc1 $f14, %lo
; CHECK-DAG: lui $6, 16672 ; ALL-DAG: lui $6, 16672
; CHECK-DAG: lui $7, 16808 ; ALL-DAG: lui $7, 16808
define void @testlowercall12() nounwind { define void @testlowercall12() nounwind {
entry: entry:
tail call void @f12(float 2.800000e+01, float 1.900000e+01, float 1.000000e+01, float 2.100000e+01) nounwind tail call void @f12(float 2.800000e+01, float 1.900000e+01, float 1.000000e+01, float 2.100000e+01) nounwind
@ -184,11 +186,11 @@ entry:
declare void @f12(float, float, float, float) declare void @f12(float, float, float, float)
; $f12, $5, $6, $7 ; $f12, $5, $6, $7
; CHECK-LABEL: testlowercall13: ; ALL-LABEL: testlowercall13:
; CHECK-DAG: lwc1 $f12, %lo ; ALL-DAG: lwc1 $f12, %lo
; CHECK-DAG: addiu $5, $zero, 83 ; ALL-DAG: addiu $5, $zero, 83
; CHECK-DAG: lui $6, 16800 ; ALL-DAG: lui $6, 16800
; CHECK-DAG: addiu $7, $zero, 25 ; ALL-DAG: addiu $7, $zero, 25
define void @testlowercall13() nounwind { define void @testlowercall13() nounwind {
entry: entry:
tail call void @f13(float 3.800000e+01, i32 83, float 2.000000e+01, i32 25) nounwind tail call void @f13(float 3.800000e+01, i32 83, float 2.000000e+01, i32 25) nounwind
@ -199,10 +201,10 @@ entry:
declare void @f13(float, i32, float, i32) declare void @f13(float, i32, float, i32)
; $f12, $f14, $7 ; $f12, $f14, $7
; CHECK-LABEL: testlowercall14: ; ALL-LABEL: testlowercall14:
; CHECK-DAG: ldc1 $f12, %lo ; ALL-DAG: ldc1 $f12, %lo
; CHECK-DAG: lwc1 $f14, %lo ; ALL-DAG: lwc1 $f14, %lo
; CHECK-DAG: lui $7, 16880 ; ALL-DAG: lui $7, 16880
define void @testlowercall14() nounwind { define void @testlowercall14() nounwind {
entry: entry:
tail call void @f14(double 3.500000e+01, float 2.900000e+01, float 3.000000e+01) nounwind tail call void @f14(double 3.500000e+01, float 2.900000e+01, float 3.000000e+01) nounwind
@ -212,15 +214,15 @@ entry:
declare void @f14(double, float, float) declare void @f14(double, float, float)
; $f12, $f14, ($6, $7) ; $f12, $f14, ($6, $7)
; CHECK-LABEL: testlowercall15: ; ALL-LABEL: testlowercall15:
; CHECK-DAG: lwc1 $f12, %lo ; ALL-DAG: lwc1 $f12, %lo
; CHECK-DAG: lwc1 $f14, %lo ; ALL-DAG: lwc1 $f14, %lo
; FP32EL-LABEL: testlowercall15:
; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}} ; NO-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}} ; NO-MFHC1-DAG: mfc1 $7, $f{{[0-9]+}}
; FP64EL-LABEL: testlowercall15:
; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}} ; HAS-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}} ; HAS-MFHC1-DAG: mfhc1 $7, $f{{[0-9]+}}
define void @testlowercall15() nounwind { define void @testlowercall15() nounwind {
entry: entry:
tail call void @f15(float 4.800000e+01, float 3.900000e+01, double 3.700000e+01) nounwind tail call void @f15(float 4.800000e+01, float 3.900000e+01, double 3.700000e+01) nounwind
@ -230,11 +232,11 @@ entry:
declare void @f15(float, float, double) declare void @f15(float, float, double)
; $4, $5, $6, $7 ; $4, $5, $6, $7
; CHECK-LABEL: testlowercall16: ; ALL-LABEL: testlowercall16:
; CHECK-DAG: addiu $4, $zero, 62 ; ALL-DAG: addiu $4, $zero, 62
; CHECK-DAG: lui $5, 16964 ; ALL-DAG: lui $5, 16964
; CHECK-DAG: addiu $6, $zero, 64 ; ALL-DAG: addiu $6, $zero, 64
; CHECK-DAG: lui $7, 16888 ; ALL-DAG: lui $7, 16888
define void @testlowercall16() nounwind { define void @testlowercall16() nounwind {
entry: entry:
tail call void @f16(i32 62, float 4.900000e+01, i32 64, float 3.100000e+01) nounwind tail call void @f16(i32 62, float 4.900000e+01, i32 64, float 3.100000e+01) nounwind
@ -244,11 +246,11 @@ entry:
declare void @f16(i32, float, i32, float) declare void @f16(i32, float, i32, float)
; $4, $5, $6, $7 ; $4, $5, $6, $7
; CHECK-LABEL: testlowercall17: ; ALL-LABEL: testlowercall17:
; CHECK-DAG: addiu $4, $zero, 72 ; ALL-DAG: addiu $4, $zero, 72
; CHECK-DAG: lui $5, 17004 ; ALL-DAG: lui $5, 17004
; CHECK-DAG: addiu $6, $zero, 74 ; ALL-DAG: addiu $6, $zero, 74
; CHECK-DAG: addiu $7, $zero, 35 ; ALL-DAG: addiu $7, $zero, 35
define void @testlowercall17() nounwind { define void @testlowercall17() nounwind {
entry: entry:
tail call void @f17(i32 72, float 5.900000e+01, i32 74, i32 35) nounwind tail call void @f17(i32 72, float 5.900000e+01, i32 74, i32 35) nounwind
@ -258,11 +260,11 @@ entry:
declare void @f17(i32, float, i32, i32) declare void @f17(i32, float, i32, i32)
; $4, $5, $6, $7 ; $4, $5, $6, $7
; CHECK-LABEL: testlowercall18: ; ALL-LABEL: testlowercall18:
; CHECK-DAG: addiu $4, $zero, 82 ; ALL-DAG: addiu $4, $zero, 82
; CHECK-DAG: addiu $5, $zero, 93 ; ALL-DAG: addiu $5, $zero, 93
; CHECK-DAG: lui $6, 16928 ; ALL-DAG: lui $6, 16928
; CHECK-DAG: addiu $7, $zero, 45 ; ALL-DAG: addiu $7, $zero, 45
define void @testlowercall18() nounwind { define void @testlowercall18() nounwind {
entry: entry:
tail call void @f18(i32 82, i32 93, float 4.000000e+01, i32 45) nounwind tail call void @f18(i32 82, i32 93, float 4.000000e+01, i32 45) nounwind
@ -273,16 +275,16 @@ declare void @f18(i32, i32, float, i32)
; $4, ($6, $7), stack ; $4, ($6, $7), stack
; CHECK-LABEL: testlowercall20: ; ALL-LABEL: testlowercall20:
; CHECK-DAG: addiu $4, $zero, 92 ; ALL-DAG: addiu $4, $zero, 92
; CHECK-DAG: sw ${{[a-z0-9]+}}, 16($sp) ; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
; CHECK-DAG: sw ${{[a-z0-9]+}}, 20($sp) ; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
; FP32EL-LABEL: testlowercall20:
; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}} ; NO-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}} ; NO-MFHC1-DAG: mfc1 $7, $f{{[0-9]+}}
; FP64EL-LABEL: testlowercall20:
; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}} ; HAS-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}} ; HAS-MFHC1-DAG: mfhc1 $7, $f{{[0-9]+}}
define void @testlowercall20() nounwind { define void @testlowercall20() nounwind {
entry: entry:
tail call void @f20(i32 92, double 2.600000e+01, double 4.700000e+01) nounwind tail call void @f20(i32 92, double 2.600000e+01, double 4.700000e+01) nounwind
@ -292,9 +294,9 @@ entry:
declare void @f20(i32, double, double) declare void @f20(i32, double, double)
; $f12, $5 ; $f12, $5
; CHECK-LABEL: testlowercall21: ; ALL-LABEL: testlowercall21:
; CHECK-DAG: lwc1 $f12, %lo ; ALL-DAG: lwc1 $f12, %lo
; CHECK-DAG: addiu $5, $zero, 103 ; ALL-DAG: addiu $5, $zero, 103
define void @testlowercall21() nounwind { define void @testlowercall21() nounwind {
entry: entry:
tail call void @f21(float 5.800000e+01, i32 103) nounwind tail call void @f21(float 5.800000e+01, i32 103) nounwind
@ -304,15 +306,15 @@ entry:
declare void @f21(float, i32) declare void @f21(float, i32)
; $f12, $5, ($6, $7) ; $f12, $5, ($6, $7)
; CHECK-LABEL: testlowercall22: ; ALL-LABEL: testlowercall22:
; CHECK-DAG: lwc1 $f12, %lo ; ALL-DAG: lwc1 $f12, %lo
; CHECK-DAG: addiu $5, $zero, 113 ; ALL-DAG: addiu $5, $zero, 113
; FP32EL-LABEL: testlowercall22:
; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}} ; NO-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}} ; NO-MFHC1-DAG: mfc1 $7, $f{{[0-9]+}}
; FP64EL-LABEL: testlowercall22:
; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}} ; HAS-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}} ; HAS-MFHC1-DAG: mfhc1 $7, $f{{[0-9]+}}
define void @testlowercall22() nounwind { define void @testlowercall22() nounwind {
entry: entry:
tail call void @f22(float 6.800000e+01, i32 113, double 5.700000e+01) nounwind tail call void @f22(float 6.800000e+01, i32 113, double 5.700000e+01) nounwind
@ -322,9 +324,9 @@ entry:
declare void @f22(float, i32, double) declare void @f22(float, i32, double)
; $f12, f6 ; $f12, f6
; CHECK-LABEL: testlowercall23: ; ALL-LABEL: testlowercall23:
; CHECK-DAG: ldc1 $f12, %lo ; ALL-DAG: ldc1 $f12, %lo
; CHECK-DAG: addiu $6, $zero, 123 ; ALL-DAG: addiu $6, $zero, 123
define void @testlowercall23() nounwind { define void @testlowercall23() nounwind {
entry: entry:
tail call void @f23(double 4.500000e+01, i32 123) nounwind tail call void @f23(double 4.500000e+01, i32 123) nounwind
@ -334,11 +336,11 @@ entry:
declare void @f23(double, i32) declare void @f23(double, i32)
; $f12,$6, stack ; $f12,$6, stack
; CHECK-LABEL: testlowercall24: ; ALL-LABEL: testlowercall24:
; CHECK-DAG: ldc1 $f12, %lo ; ALL-DAG: ldc1 $f12, %lo
; CHECK-DAG: addiu $6, $zero, 133 ; ALL-DAG: addiu $6, $zero, 133
; CHECK-DAG: sw ${{[a-z0-9]+}}, 16($sp) ; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
; CHECK-DAG: sw ${{[a-z0-9]+}}, 20($sp) ; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
define void @testlowercall24() nounwind { define void @testlowercall24() nounwind {
entry: entry:
tail call void @f24(double 5.500000e+01, i32 133, double 6.700000e+01) nounwind tail call void @f24(double 5.500000e+01, i32 133, double 6.700000e+01) nounwind
@ -347,19 +349,19 @@ entry:
declare void @f24(double, i32, double) declare void @f24(double, i32, double)
; CHECK-LABEL: testlowercall25: ; ALL-LABEL: testlowercall25:
; CHECK-DAG: lwc1 $f12, %lo ; ALL-DAG: lwc1 $f12, %lo
; CHECK-DAG: lwc1 $f14, %lo ; ALL-DAG: lwc1 $f14, %lo
; CHECK-DAG: lui $6 ; ALL-DAG: lui $6
; CHECK-DAG: lui $7 ; ALL-DAG: lui $7
; CHECK-DAG: lwc1 $f12, %lo ; ALL-DAG: lwc1 $f12, %lo
; CHECK-DAG: addiu $5, $zero, 83 ; ALL-DAG: addiu $5, $zero, 83
; CHECK-DAG: lui $6 ; ALL-DAG: lui $6
; CHECK-DAG: addiu $7, $zero, 25 ; ALL-DAG: addiu $7, $zero, 25
; CHECK-DAG: addiu $4, $zero, 82 ; ALL-DAG: addiu $4, $zero, 82
; CHECK-DAG: addiu $5, $zero, 93 ; ALL-DAG: addiu $5, $zero, 93
; CHECK-DAG: lui $6 ; ALL-DAG: lui $6
; CHECK-DAG: addiu $7, $zero, 45 ; ALL-DAG: addiu $7, $zero, 45
define void @testlowercall25() nounwind { define void @testlowercall25() nounwind {
entry: entry:
tail call void @f12(float 2.800000e+01, float 1.900000e+01, float 1.000000e+01, float 2.100000e+01) nounwind tail call void @f12(float 2.800000e+01, float 1.900000e+01, float 1.000000e+01, float 2.100000e+01) nounwind