forked from OSchip/llvm-project
[mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves
Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 llvm-svn: 212936
This commit is contained in:
Daniel Sanders
parent
3064620d0d
commit
24e08fd5c0
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@ -142,11 +142,6 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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@ -914,18 +909,6 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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@ -362,11 +362,15 @@ def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
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bitconvert>, MFC1_FM<0>;
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def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
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bitconvert>, MFC1_FM<4>;
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def MFHC1 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>,
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MFC1_FM<3>, ISA_MIPS32R2;
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def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
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def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
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MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
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def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
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MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
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let DecoderNamespace = "Mips64";
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}
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def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
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def MTHC1_D64 : MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
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def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
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let DecoderNamespace = "Mips64";
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}
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@ -521,8 +521,9 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
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unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
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unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
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if (SubIdx == Mips::sub_hi && FP64) {
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// FIXME: The .addReg(SrcReg, RegState::Implicit) is a white lie used to
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if (SubIdx == Mips::sub_hi && TM.getSubtarget<MipsSubtarget>().hasMTHC1()) {
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// FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
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// claim to read the whole 64-bits as part of a white lie used to
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// temporarily work around a widespread bug in the -mfp64 support.
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// The problem is that none of the 32-bit fpu ops mention the fact
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// that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
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@ -533,8 +534,8 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
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// We therefore pretend that it reads the bottom 32-bits to
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// artificially create a dependency and prevent the scheduler
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// changing the behaviour of the code.
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BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg(
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SrcReg, RegState::Implicit);
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BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
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.addReg(SrcReg);
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} else
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BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
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}
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@ -1,15 +1,19 @@
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=FP32 -check-prefix=CHECK
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; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=FP32 -check-prefix=CHECK
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL
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; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
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; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
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@a = external global i32
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; CHECK-LABEL: f:
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; FP32: mtc1
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; FP32: mtc1
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; FP64-DAG: mtc1
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; FP64-DAG: mthc1
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; ALL-LABEL: f:
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; NO-MFHC1: mtc1
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; NO-MFHC1: mtc1
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; HAS-MFHC1-DAG: mtc1
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; HAS-MFHC1-DAG: mthc1
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define double @f(i32 %a1, double %d) nounwind {
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entry:
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@ -18,11 +22,13 @@ entry:
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ret double %add
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}
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; CHECK-LABEL: f3:
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; FP32: mfc1
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; FP32: mfc1
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; FP64-DAG: mfc1
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; FP64-DAG: mfhc1
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; ALL-LABEL: f3:
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; NO-MFHC1: mfc1
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; NO-MFHC1: mfc1
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; HAS-MFHC1-DAG: mfc1
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; HAS-MFHC1-DAG: mfhc1
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define void @f3(double %d, i32 %a1) nounwind {
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entry:
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@ -123,7 +123,7 @@ entry:
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; 32R1-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
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; 32R2-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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; 32R2-LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
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; 32R2-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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; 32R2-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
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; 32R2-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
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@ -140,7 +140,7 @@ entry:
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; 32R1-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
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; 32R2-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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; 32R2-LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
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; 32R2-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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; 32R2-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
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; 32R2-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
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; 32R2-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
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@ -159,7 +159,7 @@ entry:
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; 32R1-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
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; 32R2-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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; 32R2-BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
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; 32R2-BE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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; 32R2-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
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; 32R2-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
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@ -225,7 +225,7 @@ entry:
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; 32R1-DAG: sw $[[R1]], 4(${{[0-9]+}})
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; 32R2-DAG: mfc1 $[[R0:[0-9]+]], $f12
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; 32R2-DAG: mfc1 $[[R1:[0-9]+]], $f13
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; 32R2-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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; 32R2-DAG: sw $[[R0]], 0(${{[0-9]+}})
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; 32R2-DAG: sw $[[R1]], 4(${{[0-9]+}})
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@ -1,12 +1,13 @@
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; RUN: llc -march=mipsel < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s
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; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=FP32EL %s
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; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck -check-prefix=FP64EL %s
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; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=ALL %s
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; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck -check-prefix=ALL %s
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; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=NO-MFHC1 %s
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-MFHC1 %s
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-MFHC1 %s
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; $f12, $f14
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; CHECK-LABEL: testlowercall0:
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; CHECK-DAG: ldc1 $f12, %lo
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; CHECK-DAG: ldc1 $f14, %lo
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; ALL-LABEL: testlowercall0:
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; ALL-DAG: ldc1 $f12, %lo
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; ALL-DAG: ldc1 $f14, %lo
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define void @testlowercall0() nounwind {
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entry:
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tail call void @f0(double 5.000000e+00, double 6.000000e+00) nounwind
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@ -16,9 +17,9 @@ entry:
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declare void @f0(double, double)
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; $f12, $f14
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; CHECK-LABEL: testlowercall1:
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; CHECK-DAG: lwc1 $f12, %lo
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; CHECK-DAG: lwc1 $f14, %lo
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; ALL-LABEL: testlowercall1:
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; ALL-DAG: lwc1 $f12, %lo
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; ALL-DAG: lwc1 $f14, %lo
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define void @testlowercall1() nounwind {
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entry:
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tail call void @f1(float 8.000000e+00, float 9.000000e+00) nounwind
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@ -28,9 +29,9 @@ entry:
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declare void @f1(float, float)
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; $f12, $f14
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; CHECK-LABEL: testlowercall2:
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; CHECK-DAG: lwc1 $f12, %lo
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; CHECK-DAG: ldc1 $f14, %lo
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; ALL-LABEL: testlowercall2:
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; ALL-DAG: lwc1 $f12, %lo
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; ALL-DAG: ldc1 $f14, %lo
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define void @testlowercall2() nounwind {
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entry:
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tail call void @f2(float 8.000000e+00, double 6.000000e+00) nounwind
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@ -40,9 +41,9 @@ entry:
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declare void @f2(float, double)
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; $f12, $f14
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; CHECK-LABEL: testlowercall3:
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; CHECK-DAG: ldc1 $f12, %lo
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; CHECK-DAG: lwc1 $f14, %lo
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; ALL-LABEL: testlowercall3:
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; ALL-DAG: ldc1 $f12, %lo
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; ALL-DAG: lwc1 $f14, %lo
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define void @testlowercall3() nounwind {
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entry:
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tail call void @f3(double 5.000000e+00, float 9.000000e+00) nounwind
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@ -52,11 +53,11 @@ entry:
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declare void @f3(double, float)
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; $4, $5, $6, $7
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; CHECK-LABEL: testlowercall4:
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; CHECK-DAG: addiu $4, $zero, 12
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; CHECK-DAG: addiu $5, $zero, 13
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; CHECK-DAG: addiu $6, $zero, 14
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; CHECK-DAG: addiu $7, $zero, 15
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; ALL-LABEL: testlowercall4:
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; ALL-DAG: addiu $4, $zero, 12
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; ALL-DAG: addiu $5, $zero, 13
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; ALL-DAG: addiu $6, $zero, 14
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; ALL-DAG: addiu $7, $zero, 15
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define void @testlowercall4() nounwind {
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entry:
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tail call void @f4(i32 12, i32 13, i32 14, i32 15) nounwind
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@ -66,11 +67,11 @@ entry:
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declare void @f4(i32, i32, i32, i32)
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; $f12, $6, stack
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; CHECK-LABEL: testlowercall5:
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; CHECK-DAG: ldc1 $f12, %lo
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; CHECK-DAG: addiu $6, $zero, 23
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; CHECK-DAG: sw ${{[a-z0-9]+}}, 16($sp)
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; CHECK-DAG: sw ${{[a-z0-9]+}}, 20($sp)
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; ALL-LABEL: testlowercall5:
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; ALL-DAG: ldc1 $f12, %lo
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; ALL-DAG: addiu $6, $zero, 23
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; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
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; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
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define void @testlowercall5() nounwind {
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entry:
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tail call void @f5(double 1.500000e+01, i32 23, double 1.700000e+01) nounwind
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@ -80,10 +81,10 @@ entry:
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declare void @f5(double, i32, double)
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; $f12, $6, $7
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; CHECK-LABEL: testlowercall6:
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; CHECK-DAG: ldc1 $f12, %lo
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; CHECK-DAG: addiu $6, $zero, 33
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; CHECK-DAG: addiu $7, $zero, 24
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; ALL-LABEL: testlowercall6:
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; ALL-DAG: ldc1 $f12, %lo
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; ALL-DAG: addiu $6, $zero, 33
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; ALL-DAG: addiu $7, $zero, 24
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define void @testlowercall6() nounwind {
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entry:
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tail call void @f6(double 2.500000e+01, i32 33, i32 24) nounwind
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@ -93,10 +94,10 @@ entry:
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declare void @f6(double, i32, i32)
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; $f12, $5, $6
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; CHECK-LABEL: testlowercall7:
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; CHECK-DAG: lwc1 $f12, %lo
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; CHECK-DAG: addiu $5, $zero, 43
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; CHECK-DAG: addiu $6, $zero, 34
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; ALL-LABEL: testlowercall7:
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; ALL-DAG: lwc1 $f12, %lo
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; ALL-DAG: addiu $5, $zero, 43
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; ALL-DAG: addiu $6, $zero, 34
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define void @testlowercall7() nounwind {
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entry:
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tail call void @f7(float 1.800000e+01, i32 43, i32 34) nounwind
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@ -106,12 +107,12 @@ entry:
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declare void @f7(float, i32, i32)
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; $4, $5, $6, stack
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; CHECK-LABEL: testlowercall8:
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; CHECK-DAG: addiu $4, $zero, 22
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; CHECK-DAG: addiu $5, $zero, 53
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; CHECK-DAG: addiu $6, $zero, 44
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; CHECK-DAG: sw ${{[a-z0-9]+}}, 16($sp)
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; CHECK-DAG: sw ${{[a-z0-9]+}}, 20($sp)
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; ALL-LABEL: testlowercall8:
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; ALL-DAG: addiu $4, $zero, 22
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; ALL-DAG: addiu $5, $zero, 53
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; ALL-DAG: addiu $6, $zero, 44
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; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
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; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
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define void @testlowercall8() nounwind {
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entry:
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tail call void @f8(i32 22, i32 53, i32 44, double 4.000000e+00) nounwind
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@ -121,11 +122,11 @@ entry:
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declare void @f8(i32, i32, i32, double)
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; $4, $5, $6, $7
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; CHECK-LABEL: testlowercall9:
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; CHECK-DAG: addiu $4, $zero, 32
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; CHECK-DAG: addiu $5, $zero, 63
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; CHECK-DAG: addiu $6, $zero, 54
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; CHECK-DAG: lui $7, 16688
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; ALL-LABEL: testlowercall9:
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; ALL-DAG: addiu $4, $zero, 32
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; ALL-DAG: addiu $5, $zero, 63
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; ALL-DAG: addiu $6, $zero, 54
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; ALL-DAG: lui $7, 16688
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define void @testlowercall9() nounwind {
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entry:
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tail call void @f9(i32 32, i32 63, i32 54, float 1.100000e+01) nounwind
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@ -135,15 +136,16 @@ entry:
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declare void @f9(i32, i32, i32, float)
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; $4, $5, ($6, $7)
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; CHECK-LABEL: testlowercall10:
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; CHECK-DAG: addiu $4, $zero, 42
|
||||
; CHECK-DAG: addiu $5, $zero, 73
|
||||
; FP32EL-LABEL: testlowercall10:
|
||||
; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}}
|
||||
; FP64EL-LABEL: testlowercall10:
|
||||
; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}}
|
||||
; ALL-LABEL: testlowercall10:
|
||||
|
||||
; ALL-DAG: addiu $4, $zero, 42
|
||||
; ALL-DAG: addiu $5, $zero, 73
|
||||
|
||||
; NO-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; NO-MFHC1-DAG: mfc1 $7, $f{{[0-9]+}}
|
||||
|
||||
; HAS-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; HAS-MFHC1-DAG: mfhc1 $7, $f{{[0-9]+}}
|
||||
define void @testlowercall10() nounwind {
|
||||
entry:
|
||||
tail call void @f10(i32 42, i32 73, double 2.700000e+01) nounwind
|
||||
|
|
@ -153,14 +155,14 @@ entry:
|
|||
declare void @f10(i32, i32, double)
|
||||
|
||||
; $4, ($6, $7)
|
||||
; CHECK-LABEL: testlowercall11:
|
||||
; CHECK-DAG: addiu $4, $zero, 52
|
||||
; FP32EL-LABEL: testlowercall11:
|
||||
; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}}
|
||||
; FP64EL-LABEL: testlowercall11:
|
||||
; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}}
|
||||
; ALL-LABEL: testlowercall11:
|
||||
; ALL-DAG: addiu $4, $zero, 52
|
||||
|
||||
; NO-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; NO-MFHC1-DAG: mfc1 $7, $f{{[0-9]+}}
|
||||
|
||||
; HAS-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; HAS-MFHC1-DAG: mfhc1 $7, $f{{[0-9]+}}
|
||||
define void @testlowercall11() nounwind {
|
||||
entry:
|
||||
tail call void @f11(i32 52, double 1.600000e+01) nounwind
|
||||
|
|
@ -170,11 +172,11 @@ entry:
|
|||
declare void @f11(i32, double)
|
||||
|
||||
; $f12, $f14, $6, $7
|
||||
; CHECK-LABEL: testlowercall12:
|
||||
; CHECK-DAG: lwc1 $f12, %lo
|
||||
; CHECK-DAG: lwc1 $f14, %lo
|
||||
; CHECK-DAG: lui $6, 16672
|
||||
; CHECK-DAG: lui $7, 16808
|
||||
; ALL-LABEL: testlowercall12:
|
||||
; ALL-DAG: lwc1 $f12, %lo
|
||||
; ALL-DAG: lwc1 $f14, %lo
|
||||
; ALL-DAG: lui $6, 16672
|
||||
; ALL-DAG: lui $7, 16808
|
||||
define void @testlowercall12() nounwind {
|
||||
entry:
|
||||
tail call void @f12(float 2.800000e+01, float 1.900000e+01, float 1.000000e+01, float 2.100000e+01) nounwind
|
||||
|
|
@ -184,11 +186,11 @@ entry:
|
|||
declare void @f12(float, float, float, float)
|
||||
|
||||
; $f12, $5, $6, $7
|
||||
; CHECK-LABEL: testlowercall13:
|
||||
; CHECK-DAG: lwc1 $f12, %lo
|
||||
; CHECK-DAG: addiu $5, $zero, 83
|
||||
; CHECK-DAG: lui $6, 16800
|
||||
; CHECK-DAG: addiu $7, $zero, 25
|
||||
; ALL-LABEL: testlowercall13:
|
||||
; ALL-DAG: lwc1 $f12, %lo
|
||||
; ALL-DAG: addiu $5, $zero, 83
|
||||
; ALL-DAG: lui $6, 16800
|
||||
; ALL-DAG: addiu $7, $zero, 25
|
||||
define void @testlowercall13() nounwind {
|
||||
entry:
|
||||
tail call void @f13(float 3.800000e+01, i32 83, float 2.000000e+01, i32 25) nounwind
|
||||
|
|
@ -199,10 +201,10 @@ entry:
|
|||
declare void @f13(float, i32, float, i32)
|
||||
|
||||
; $f12, $f14, $7
|
||||
; CHECK-LABEL: testlowercall14:
|
||||
; CHECK-DAG: ldc1 $f12, %lo
|
||||
; CHECK-DAG: lwc1 $f14, %lo
|
||||
; CHECK-DAG: lui $7, 16880
|
||||
; ALL-LABEL: testlowercall14:
|
||||
; ALL-DAG: ldc1 $f12, %lo
|
||||
; ALL-DAG: lwc1 $f14, %lo
|
||||
; ALL-DAG: lui $7, 16880
|
||||
define void @testlowercall14() nounwind {
|
||||
entry:
|
||||
tail call void @f14(double 3.500000e+01, float 2.900000e+01, float 3.000000e+01) nounwind
|
||||
|
|
@ -212,15 +214,15 @@ entry:
|
|||
declare void @f14(double, float, float)
|
||||
|
||||
; $f12, $f14, ($6, $7)
|
||||
; CHECK-LABEL: testlowercall15:
|
||||
; CHECK-DAG: lwc1 $f12, %lo
|
||||
; CHECK-DAG: lwc1 $f14, %lo
|
||||
; FP32EL-LABEL: testlowercall15:
|
||||
; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}}
|
||||
; FP64EL-LABEL: testlowercall15:
|
||||
; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}}
|
||||
; ALL-LABEL: testlowercall15:
|
||||
; ALL-DAG: lwc1 $f12, %lo
|
||||
; ALL-DAG: lwc1 $f14, %lo
|
||||
|
||||
; NO-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; NO-MFHC1-DAG: mfc1 $7, $f{{[0-9]+}}
|
||||
|
||||
; HAS-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; HAS-MFHC1-DAG: mfhc1 $7, $f{{[0-9]+}}
|
||||
define void @testlowercall15() nounwind {
|
||||
entry:
|
||||
tail call void @f15(float 4.800000e+01, float 3.900000e+01, double 3.700000e+01) nounwind
|
||||
|
|
@ -230,11 +232,11 @@ entry:
|
|||
declare void @f15(float, float, double)
|
||||
|
||||
; $4, $5, $6, $7
|
||||
; CHECK-LABEL: testlowercall16:
|
||||
; CHECK-DAG: addiu $4, $zero, 62
|
||||
; CHECK-DAG: lui $5, 16964
|
||||
; CHECK-DAG: addiu $6, $zero, 64
|
||||
; CHECK-DAG: lui $7, 16888
|
||||
; ALL-LABEL: testlowercall16:
|
||||
; ALL-DAG: addiu $4, $zero, 62
|
||||
; ALL-DAG: lui $5, 16964
|
||||
; ALL-DAG: addiu $6, $zero, 64
|
||||
; ALL-DAG: lui $7, 16888
|
||||
define void @testlowercall16() nounwind {
|
||||
entry:
|
||||
tail call void @f16(i32 62, float 4.900000e+01, i32 64, float 3.100000e+01) nounwind
|
||||
|
|
@ -244,11 +246,11 @@ entry:
|
|||
declare void @f16(i32, float, i32, float)
|
||||
|
||||
; $4, $5, $6, $7
|
||||
; CHECK-LABEL: testlowercall17:
|
||||
; CHECK-DAG: addiu $4, $zero, 72
|
||||
; CHECK-DAG: lui $5, 17004
|
||||
; CHECK-DAG: addiu $6, $zero, 74
|
||||
; CHECK-DAG: addiu $7, $zero, 35
|
||||
; ALL-LABEL: testlowercall17:
|
||||
; ALL-DAG: addiu $4, $zero, 72
|
||||
; ALL-DAG: lui $5, 17004
|
||||
; ALL-DAG: addiu $6, $zero, 74
|
||||
; ALL-DAG: addiu $7, $zero, 35
|
||||
define void @testlowercall17() nounwind {
|
||||
entry:
|
||||
tail call void @f17(i32 72, float 5.900000e+01, i32 74, i32 35) nounwind
|
||||
|
|
@ -258,11 +260,11 @@ entry:
|
|||
declare void @f17(i32, float, i32, i32)
|
||||
|
||||
; $4, $5, $6, $7
|
||||
; CHECK-LABEL: testlowercall18:
|
||||
; CHECK-DAG: addiu $4, $zero, 82
|
||||
; CHECK-DAG: addiu $5, $zero, 93
|
||||
; CHECK-DAG: lui $6, 16928
|
||||
; CHECK-DAG: addiu $7, $zero, 45
|
||||
; ALL-LABEL: testlowercall18:
|
||||
; ALL-DAG: addiu $4, $zero, 82
|
||||
; ALL-DAG: addiu $5, $zero, 93
|
||||
; ALL-DAG: lui $6, 16928
|
||||
; ALL-DAG: addiu $7, $zero, 45
|
||||
define void @testlowercall18() nounwind {
|
||||
entry:
|
||||
tail call void @f18(i32 82, i32 93, float 4.000000e+01, i32 45) nounwind
|
||||
|
|
@ -273,16 +275,16 @@ declare void @f18(i32, i32, float, i32)
|
|||
|
||||
|
||||
; $4, ($6, $7), stack
|
||||
; CHECK-LABEL: testlowercall20:
|
||||
; CHECK-DAG: addiu $4, $zero, 92
|
||||
; CHECK-DAG: sw ${{[a-z0-9]+}}, 16($sp)
|
||||
; CHECK-DAG: sw ${{[a-z0-9]+}}, 20($sp)
|
||||
; FP32EL-LABEL: testlowercall20:
|
||||
; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}}
|
||||
; FP64EL-LABEL: testlowercall20:
|
||||
; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}}
|
||||
; ALL-LABEL: testlowercall20:
|
||||
; ALL-DAG: addiu $4, $zero, 92
|
||||
; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
|
||||
; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
|
||||
|
||||
; NO-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; NO-MFHC1-DAG: mfc1 $7, $f{{[0-9]+}}
|
||||
|
||||
; HAS-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; HAS-MFHC1-DAG: mfhc1 $7, $f{{[0-9]+}}
|
||||
define void @testlowercall20() nounwind {
|
||||
entry:
|
||||
tail call void @f20(i32 92, double 2.600000e+01, double 4.700000e+01) nounwind
|
||||
|
|
@ -292,9 +294,9 @@ entry:
|
|||
declare void @f20(i32, double, double)
|
||||
|
||||
; $f12, $5
|
||||
; CHECK-LABEL: testlowercall21:
|
||||
; CHECK-DAG: lwc1 $f12, %lo
|
||||
; CHECK-DAG: addiu $5, $zero, 103
|
||||
; ALL-LABEL: testlowercall21:
|
||||
; ALL-DAG: lwc1 $f12, %lo
|
||||
; ALL-DAG: addiu $5, $zero, 103
|
||||
define void @testlowercall21() nounwind {
|
||||
entry:
|
||||
tail call void @f21(float 5.800000e+01, i32 103) nounwind
|
||||
|
|
@ -304,15 +306,15 @@ entry:
|
|||
declare void @f21(float, i32)
|
||||
|
||||
; $f12, $5, ($6, $7)
|
||||
; CHECK-LABEL: testlowercall22:
|
||||
; CHECK-DAG: lwc1 $f12, %lo
|
||||
; CHECK-DAG: addiu $5, $zero, 113
|
||||
; FP32EL-LABEL: testlowercall22:
|
||||
; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}}
|
||||
; FP64EL-LABEL: testlowercall22:
|
||||
; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}}
|
||||
; ALL-LABEL: testlowercall22:
|
||||
; ALL-DAG: lwc1 $f12, %lo
|
||||
; ALL-DAG: addiu $5, $zero, 113
|
||||
|
||||
; NO-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; NO-MFHC1-DAG: mfc1 $7, $f{{[0-9]+}}
|
||||
|
||||
; HAS-MFHC1-DAG: mfc1 $6, $f{{[0-9]+}}
|
||||
; HAS-MFHC1-DAG: mfhc1 $7, $f{{[0-9]+}}
|
||||
define void @testlowercall22() nounwind {
|
||||
entry:
|
||||
tail call void @f22(float 6.800000e+01, i32 113, double 5.700000e+01) nounwind
|
||||
|
|
@ -322,9 +324,9 @@ entry:
|
|||
declare void @f22(float, i32, double)
|
||||
|
||||
; $f12, f6
|
||||
; CHECK-LABEL: testlowercall23:
|
||||
; CHECK-DAG: ldc1 $f12, %lo
|
||||
; CHECK-DAG: addiu $6, $zero, 123
|
||||
; ALL-LABEL: testlowercall23:
|
||||
; ALL-DAG: ldc1 $f12, %lo
|
||||
; ALL-DAG: addiu $6, $zero, 123
|
||||
define void @testlowercall23() nounwind {
|
||||
entry:
|
||||
tail call void @f23(double 4.500000e+01, i32 123) nounwind
|
||||
|
|
@ -334,11 +336,11 @@ entry:
|
|||
declare void @f23(double, i32)
|
||||
|
||||
; $f12,$6, stack
|
||||
; CHECK-LABEL: testlowercall24:
|
||||
; CHECK-DAG: ldc1 $f12, %lo
|
||||
; CHECK-DAG: addiu $6, $zero, 133
|
||||
; CHECK-DAG: sw ${{[a-z0-9]+}}, 16($sp)
|
||||
; CHECK-DAG: sw ${{[a-z0-9]+}}, 20($sp)
|
||||
; ALL-LABEL: testlowercall24:
|
||||
; ALL-DAG: ldc1 $f12, %lo
|
||||
; ALL-DAG: addiu $6, $zero, 133
|
||||
; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
|
||||
; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
|
||||
define void @testlowercall24() nounwind {
|
||||
entry:
|
||||
tail call void @f24(double 5.500000e+01, i32 133, double 6.700000e+01) nounwind
|
||||
|
|
@ -347,19 +349,19 @@ entry:
|
|||
|
||||
declare void @f24(double, i32, double)
|
||||
|
||||
; CHECK-LABEL: testlowercall25:
|
||||
; CHECK-DAG: lwc1 $f12, %lo
|
||||
; CHECK-DAG: lwc1 $f14, %lo
|
||||
; CHECK-DAG: lui $6
|
||||
; CHECK-DAG: lui $7
|
||||
; CHECK-DAG: lwc1 $f12, %lo
|
||||
; CHECK-DAG: addiu $5, $zero, 83
|
||||
; CHECK-DAG: lui $6
|
||||
; CHECK-DAG: addiu $7, $zero, 25
|
||||
; CHECK-DAG: addiu $4, $zero, 82
|
||||
; CHECK-DAG: addiu $5, $zero, 93
|
||||
; CHECK-DAG: lui $6
|
||||
; CHECK-DAG: addiu $7, $zero, 45
|
||||
; ALL-LABEL: testlowercall25:
|
||||
; ALL-DAG: lwc1 $f12, %lo
|
||||
; ALL-DAG: lwc1 $f14, %lo
|
||||
; ALL-DAG: lui $6
|
||||
; ALL-DAG: lui $7
|
||||
; ALL-DAG: lwc1 $f12, %lo
|
||||
; ALL-DAG: addiu $5, $zero, 83
|
||||
; ALL-DAG: lui $6
|
||||
; ALL-DAG: addiu $7, $zero, 25
|
||||
; ALL-DAG: addiu $4, $zero, 82
|
||||
; ALL-DAG: addiu $5, $zero, 93
|
||||
; ALL-DAG: lui $6
|
||||
; ALL-DAG: addiu $7, $zero, 45
|
||||
define void @testlowercall25() nounwind {
|
||||
entry:
|
||||
tail call void @f12(float 2.800000e+01, float 1.900000e+01, float 1.000000e+01, float 2.100000e+01) nounwind
|
||||
|
|
|
|||
Loading…
Reference in New Issue