forked from OSchip/llvm-project
[LoongArch] Support Load and Store with 14-bit signed immediate operands
Differential Revision: https://reviews.llvm.org/D131954
This commit is contained in:
gonglingqin
parent
0e7971154e
commit
2492bdb2c6
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@ -126,7 +126,8 @@ def simm12 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isInt<12>(Imm);}]> {
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let DecoderMethod = "decodeSImmOperand<12>";
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}
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def simm14_lsl2 : Operand<GRLenVT> {
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def simm14_lsl2 : Operand<GRLenVT>,
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ImmLeaf<GRLenVT, [{return isShiftedInt<14,2>(Imm);}]> {
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let ParserMatchClass = SImmAsmOperand<14, "lsl2">;
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let EncoderMethod = "getImmOpValueAsr2";
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let DecoderMethod = "decodeSImmOperand<14, 2>";
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@ -962,6 +963,18 @@ defm : StPat<truncstorei32, ST_W, GPR, i64>;
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defm : StPat<store, ST_D, GPR, i64>;
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} // Predicates = [IsLA64]
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let Predicates = [IsLA64] in {
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def : Pat<(i64 (sextloadi32 (AddLike BaseAddr:$rj, simm14_lsl2:$imm14))),
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(LDPTR_W BaseAddr:$rj, simm14_lsl2:$imm14)>;
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def : Pat<(i64 (load (AddLike BaseAddr:$rj, simm14_lsl2:$imm14))),
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(LDPTR_D BaseAddr:$rj, simm14_lsl2:$imm14)>;
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def : Pat<(truncstorei32 (i64 GPR:$rd),
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(AddLike BaseAddr:$rj, simm14_lsl2:$imm14)),
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(STPTR_W GPR:$rd, BaseAddr:$rj, simm14_lsl2:$imm14)>;
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def : Pat<(store (i64 GPR:$rd), (AddLike BaseAddr:$rj, simm14_lsl2:$imm14)),
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(STPTR_D GPR:$rd, BaseAddr:$rj, simm14_lsl2:$imm14)>;
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} // Predicates = [IsLA64]
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// LA64 register-register-addressed stores
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let Predicates = [IsLA64] in {
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class RegRegStPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy>
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@ -0,0 +1,123 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
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; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
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;; Check that ldptr.w is not emitted for small offsets.
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define signext i32 @ldptr_w_too_small_offset(ptr %p) nounwind {
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; LA32-LABEL: ldptr_w_too_small_offset:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ld.w $a0, $a0, 2044
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ldptr_w_too_small_offset:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ld.w $a0, $a0, 2044
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; LA64-NEXT: ret
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entry:
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%addr = getelementptr inbounds i32, ptr %p, i64 511
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%val = load i32, ptr %addr, align 4
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ret i32 %val
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}
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;; Check that ldptr.w is emitted for applicable offsets.
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define signext i32 @ldptr_w(ptr %p) nounwind {
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; LA32-LABEL: ldptr_w:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a1, $zero, 2048
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; LA32-NEXT: add.w $a0, $a0, $a1
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; LA32-NEXT: ld.w $a0, $a0, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ldptr_w:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ldptr.w $a0, $a0, 2048
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; LA64-NEXT: ret
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entry:
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%addr = getelementptr inbounds i32, ptr %p, i64 512
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%val = load i32, ptr %addr, align 4
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ret i32 %val
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}
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;; Check that ldptr.w is not emitted for out-of-range offsets.
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define signext i32 @ldptr_w_too_big_offset(ptr %p) nounwind {
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; LA32-LABEL: ldptr_w_too_big_offset:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: lu12i.w $a1, 8
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; LA32-NEXT: add.w $a0, $a0, $a1
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; LA32-NEXT: ld.w $a0, $a0, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ldptr_w_too_big_offset:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: lu12i.w $a1, 8
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; LA64-NEXT: ldx.w $a0, $a0, $a1
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; LA64-NEXT: ret
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entry:
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%addr = getelementptr inbounds i32, ptr %p, i64 8192
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%val = load i32, ptr %addr, align 4
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ret i32 %val
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}
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;; Check that ldptr.d is not emitted for small offsets.
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define i64 @ldptr_d_too_small_offset(ptr %p) nounwind {
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; LA32-LABEL: ldptr_d_too_small_offset:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ld.w $a2, $a0, 2040
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; LA32-NEXT: ld.w $a1, $a0, 2044
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; LA32-NEXT: move $a0, $a2
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ldptr_d_too_small_offset:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ld.d $a0, $a0, 2040
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; LA64-NEXT: ret
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entry:
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%addr = getelementptr inbounds i64, ptr %p, i64 255
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%val = load i64, ptr %addr, align 8
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ret i64 %val
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}
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;; Check that ldptr.d is emitted for applicable offsets.
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define i64 @ldptr_d(ptr %p) nounwind {
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; LA32-LABEL: ldptr_d:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a1, $zero, 2052
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; LA32-NEXT: add.w $a1, $a0, $a1
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; LA32-NEXT: ori $a2, $zero, 2048
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; LA32-NEXT: add.w $a0, $a0, $a2
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; LA32-NEXT: ld.w $a0, $a0, 0
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; LA32-NEXT: ld.w $a1, $a1, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ldptr_d:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ldptr.d $a0, $a0, 2048
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; LA64-NEXT: ret
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entry:
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%addr = getelementptr inbounds i64, ptr %p, i64 256
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%val = load i64, ptr %addr, align 8
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ret i64 %val
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}
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;; Check that ldptr.d is not emitted for out-of-range offsets.
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define i64 @ldptr_d_too_big_offset(ptr %p) nounwind {
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; LA32-LABEL: ldptr_d_too_big_offset:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: lu12i.w $a1, 8
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; LA32-NEXT: ori $a2, $a1, 4
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; LA32-NEXT: add.w $a2, $a0, $a2
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; LA32-NEXT: add.w $a0, $a0, $a1
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; LA32-NEXT: ld.w $a0, $a0, 0
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; LA32-NEXT: ld.w $a1, $a2, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ldptr_d_too_big_offset:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: lu12i.w $a1, 8
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; LA64-NEXT: ldx.d $a0, $a0, $a1
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; LA64-NEXT: ret
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entry:
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%addr = getelementptr inbounds i64, ptr %p, i64 4096
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%val = load i64, ptr %addr, align 8
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ret i64 %val
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}
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@ -0,0 +1,116 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
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; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
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;; Check that stptr.w is not emitted for small offsets.
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define void @stptr_w_too_small_offset(ptr %p, i32 signext %val) nounwind {
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; LA32-LABEL: stptr_w_too_small_offset:
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; LA32: # %bb.0:
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; LA32-NEXT: st.w $a1, $a0, 2044
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; LA32-NEXT: ret
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;
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; LA64-LABEL: stptr_w_too_small_offset:
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; LA64: # %bb.0:
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; LA64-NEXT: st.w $a1, $a0, 2044
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; LA64-NEXT: ret
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%addr = getelementptr inbounds i32, ptr %p, i64 511
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store i32 %val, ptr %addr, align 4
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ret void
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}
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;; Check that stptr.w is emitted for applicable offsets.
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define void @stptr_w(ptr %p, i32 signext %val) nounwind {
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; LA32-LABEL: stptr_w:
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; LA32: # %bb.0:
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; LA32-NEXT: ori $a2, $zero, 2048
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; LA32-NEXT: add.w $a0, $a0, $a2
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; LA32-NEXT: st.w $a1, $a0, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: stptr_w:
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; LA64: # %bb.0:
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; LA64-NEXT: stptr.w $a1, $a0, 2048
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; LA64-NEXT: ret
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%addr = getelementptr inbounds i32, ptr %p, i64 512
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store i32 %val, ptr %addr, align 4
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ret void
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}
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;; Check that stptr.w is not emitted for out-of-range offsets.
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define void @stptr_w_too_big_offset(ptr %p, i32 signext %val) nounwind {
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; LA32-LABEL: stptr_w_too_big_offset:
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; LA32: # %bb.0:
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; LA32-NEXT: lu12i.w $a2, 8
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; LA32-NEXT: add.w $a0, $a0, $a2
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; LA32-NEXT: st.w $a1, $a0, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: stptr_w_too_big_offset:
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; LA64: # %bb.0:
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; LA64-NEXT: lu12i.w $a2, 8
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; LA64-NEXT: stx.w $a1, $a0, $a2
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; LA64-NEXT: ret
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%addr = getelementptr inbounds i32, ptr %p, i64 8192
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store i32 %val, ptr %addr, align 4
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ret void
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}
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;; Check that stptr.d is not emitted for small offsets.
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define void @stptr_d_too_small_offset(ptr %p, i64 %val) nounwind {
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; LA32-LABEL: stptr_d_too_small_offset:
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; LA32: # %bb.0:
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; LA32-NEXT: st.w $a2, $a0, 2044
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; LA32-NEXT: st.w $a1, $a0, 2040
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; LA32-NEXT: ret
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;
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; LA64-LABEL: stptr_d_too_small_offset:
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; LA64: # %bb.0:
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; LA64-NEXT: st.d $a1, $a0, 2040
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; LA64-NEXT: ret
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%addr = getelementptr inbounds i64, ptr %p, i64 255
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store i64 %val, ptr %addr, align 8
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ret void
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}
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;; Check that stptr.d is emitted for applicable offsets.
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define void @stptr_d(ptr %p, i64 %val) nounwind {
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; LA32-LABEL: stptr_d:
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; LA32: # %bb.0:
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; LA32-NEXT: ori $a3, $zero, 2052
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; LA32-NEXT: add.w $a3, $a0, $a3
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; LA32-NEXT: st.w $a2, $a3, 0
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; LA32-NEXT: ori $a2, $zero, 2048
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; LA32-NEXT: add.w $a0, $a0, $a2
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; LA32-NEXT: st.w $a1, $a0, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: stptr_d:
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; LA64: # %bb.0:
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; LA64-NEXT: stptr.d $a1, $a0, 2048
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; LA64-NEXT: ret
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%addr = getelementptr inbounds i64, ptr %p, i64 256
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store i64 %val, ptr %addr, align 8
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ret void
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}
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;; Check that stptr.d is not emitted for out-of-range offsets.
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define void @stptr_d_too_big_offset(ptr %p, i64 %val) nounwind {
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; LA32-LABEL: stptr_d_too_big_offset:
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; LA32: # %bb.0:
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; LA32-NEXT: lu12i.w $a3, 8
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; LA32-NEXT: add.w $a4, $a0, $a3
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; LA32-NEXT: st.w $a1, $a4, 0
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; LA32-NEXT: ori $a1, $a3, 4
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; LA32-NEXT: add.w $a0, $a0, $a1
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; LA32-NEXT: st.w $a2, $a0, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: stptr_d_too_big_offset:
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; LA64: # %bb.0:
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; LA64-NEXT: lu12i.w $a2, 8
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; LA64-NEXT: stx.d $a1, $a0, $a2
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; LA64-NEXT: ret
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%addr = getelementptr inbounds i64, ptr %p, i64 4096
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store i64 %val, ptr %addr, align 8
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ret void
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}
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