From 2492bdb2c67a865375cac246f584a9a8686ffa0b Mon Sep 17 00:00:00 2001
From: gonglingqin <gonglingqin@loongson.cn>
Date: Mon, 22 Aug 2022 10:58:29 +0800
Subject: [PATCH] [LoongArch] Support Load and Store with 14-bit signed
 immediate operands

Differential Revision: https://reviews.llvm.org/D131954
---
 .../Target/LoongArch/LoongArchInstrInfo.td    |  15 ++-
 llvm/test/CodeGen/LoongArch/ldptr.ll          | 123 ++++++++++++++++++
 llvm/test/CodeGen/LoongArch/stptr.ll          | 116 +++++++++++++++++
 3 files changed, 253 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/LoongArch/ldptr.ll
 create mode 100644 llvm/test/CodeGen/LoongArch/stptr.ll

diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index 29c3255aa918..4197cbb5f4e9 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -126,7 +126,8 @@ def simm12 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isInt<12>(Imm);}]> {
   let DecoderMethod = "decodeSImmOperand<12>";
 }
 
-def simm14_lsl2 : Operand<GRLenVT> {
+def simm14_lsl2 : Operand<GRLenVT>,
+    ImmLeaf<GRLenVT, [{return isShiftedInt<14,2>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<14, "lsl2">;
   let EncoderMethod = "getImmOpValueAsr2";
   let DecoderMethod = "decodeSImmOperand<14, 2>";
@@ -962,6 +963,18 @@ defm : StPat<truncstorei32, ST_W, GPR, i64>;
 defm : StPat<store, ST_D, GPR, i64>;
 } // Predicates = [IsLA64]
 
+let Predicates = [IsLA64] in {
+def : Pat<(i64 (sextloadi32 (AddLike BaseAddr:$rj, simm14_lsl2:$imm14))),
+          (LDPTR_W BaseAddr:$rj, simm14_lsl2:$imm14)>;
+def : Pat<(i64 (load (AddLike BaseAddr:$rj, simm14_lsl2:$imm14))),
+          (LDPTR_D BaseAddr:$rj, simm14_lsl2:$imm14)>;
+def : Pat<(truncstorei32 (i64 GPR:$rd),
+                         (AddLike BaseAddr:$rj, simm14_lsl2:$imm14)),
+          (STPTR_W GPR:$rd, BaseAddr:$rj, simm14_lsl2:$imm14)>;
+def : Pat<(store (i64 GPR:$rd), (AddLike BaseAddr:$rj, simm14_lsl2:$imm14)),
+          (STPTR_D GPR:$rd, BaseAddr:$rj, simm14_lsl2:$imm14)>;
+} // Predicates = [IsLA64]
+
 // LA64 register-register-addressed stores
 let Predicates = [IsLA64] in {
 class RegRegStPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy>
diff --git a/llvm/test/CodeGen/LoongArch/ldptr.ll b/llvm/test/CodeGen/LoongArch/ldptr.ll
new file mode 100644
index 000000000000..81254164e7e5
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/ldptr.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+;; Check that ldptr.w is not emitted for small offsets.
+define signext i32 @ldptr_w_too_small_offset(ptr %p) nounwind {
+; LA32-LABEL: ldptr_w_too_small_offset:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    ld.w $a0, $a0, 2044
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ldptr_w_too_small_offset:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    ld.w $a0, $a0, 2044
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i32, ptr %p, i64 511
+  %val = load i32, ptr %addr, align 4
+  ret i32 %val
+}
+
+;; Check that ldptr.w is emitted for applicable offsets.
+define signext i32 @ldptr_w(ptr %p) nounwind {
+; LA32-LABEL: ldptr_w:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    ori $a1, $zero, 2048
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ldptr_w:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    ldptr.w $a0, $a0, 2048
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i32, ptr %p, i64 512
+  %val = load i32, ptr %addr, align 4
+  ret i32 %val
+}
+
+;; Check that ldptr.w is not emitted for out-of-range offsets.
+define signext i32 @ldptr_w_too_big_offset(ptr %p) nounwind {
+; LA32-LABEL: ldptr_w_too_big_offset:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    lu12i.w $a1, 8
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ldptr_w_too_big_offset:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    lu12i.w $a1, 8
+; LA64-NEXT:    ldx.w $a0, $a0, $a1
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i32, ptr %p, i64 8192
+  %val = load i32, ptr %addr, align 4
+  ret i32 %val
+}
+
+;; Check that ldptr.d is not emitted for small offsets.
+define i64 @ldptr_d_too_small_offset(ptr %p) nounwind {
+; LA32-LABEL: ldptr_d_too_small_offset:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    ld.w $a2, $a0, 2040
+; LA32-NEXT:    ld.w $a1, $a0, 2044
+; LA32-NEXT:    move $a0, $a2
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ldptr_d_too_small_offset:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    ld.d $a0, $a0, 2040
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i64, ptr %p, i64 255
+  %val = load i64, ptr %addr, align 8
+  ret i64 %val
+}
+
+;; Check that ldptr.d is emitted for applicable offsets.
+define i64 @ldptr_d(ptr %p) nounwind {
+; LA32-LABEL: ldptr_d:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    ori $a1, $zero, 2052
+; LA32-NEXT:    add.w $a1, $a0, $a1
+; LA32-NEXT:    ori $a2, $zero, 2048
+; LA32-NEXT:    add.w $a0, $a0, $a2
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    ld.w $a1, $a1, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ldptr_d:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    ldptr.d $a0, $a0, 2048
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i64, ptr %p, i64 256
+  %val = load i64, ptr %addr, align 8
+  ret i64 %val
+}
+
+;; Check that ldptr.d is not emitted for out-of-range offsets.
+define i64 @ldptr_d_too_big_offset(ptr %p) nounwind {
+; LA32-LABEL: ldptr_d_too_big_offset:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    lu12i.w $a1, 8
+; LA32-NEXT:    ori $a2, $a1, 4
+; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    ld.w $a1, $a2, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ldptr_d_too_big_offset:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    lu12i.w $a1, 8
+; LA64-NEXT:    ldx.d $a0, $a0, $a1
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i64, ptr %p, i64 4096
+  %val = load i64, ptr %addr, align 8
+  ret i64 %val
+}
diff --git a/llvm/test/CodeGen/LoongArch/stptr.ll b/llvm/test/CodeGen/LoongArch/stptr.ll
new file mode 100644
index 000000000000..5b6998b08731
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/stptr.ll
@@ -0,0 +1,116 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+;; Check that stptr.w is not emitted for small offsets.
+define void @stptr_w_too_small_offset(ptr %p, i32 signext %val) nounwind {
+; LA32-LABEL: stptr_w_too_small_offset:
+; LA32:       # %bb.0:
+; LA32-NEXT:    st.w $a1, $a0, 2044
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: stptr_w_too_small_offset:
+; LA64:       # %bb.0:
+; LA64-NEXT:    st.w $a1, $a0, 2044
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i32, ptr %p, i64 511
+  store i32 %val, ptr %addr, align 4
+  ret void
+}
+
+;; Check that stptr.w is emitted for applicable offsets.
+define void @stptr_w(ptr %p, i32 signext %val) nounwind {
+; LA32-LABEL: stptr_w:
+; LA32:       # %bb.0:
+; LA32-NEXT:    ori $a2, $zero, 2048
+; LA32-NEXT:    add.w $a0, $a0, $a2
+; LA32-NEXT:    st.w $a1, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: stptr_w:
+; LA64:       # %bb.0:
+; LA64-NEXT:    stptr.w $a1, $a0, 2048
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i32, ptr %p, i64 512
+  store i32 %val, ptr %addr, align 4
+  ret void
+}
+
+;; Check that stptr.w is not emitted for out-of-range offsets.
+define void @stptr_w_too_big_offset(ptr %p, i32 signext %val) nounwind {
+; LA32-LABEL: stptr_w_too_big_offset:
+; LA32:       # %bb.0:
+; LA32-NEXT:    lu12i.w $a2, 8
+; LA32-NEXT:    add.w $a0, $a0, $a2
+; LA32-NEXT:    st.w $a1, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: stptr_w_too_big_offset:
+; LA64:       # %bb.0:
+; LA64-NEXT:    lu12i.w $a2, 8
+; LA64-NEXT:    stx.w $a1, $a0, $a2
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i32, ptr %p, i64 8192
+  store i32 %val, ptr %addr, align 4
+  ret void
+}
+
+;; Check that stptr.d is not emitted for small offsets.
+define void @stptr_d_too_small_offset(ptr %p, i64 %val) nounwind {
+; LA32-LABEL: stptr_d_too_small_offset:
+; LA32:       # %bb.0:
+; LA32-NEXT:    st.w $a2, $a0, 2044
+; LA32-NEXT:    st.w $a1, $a0, 2040
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: stptr_d_too_small_offset:
+; LA64:       # %bb.0:
+; LA64-NEXT:    st.d $a1, $a0, 2040
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i64, ptr %p, i64 255
+  store i64 %val, ptr %addr, align 8
+  ret void
+}
+
+;; Check that stptr.d is emitted for applicable offsets.
+define void @stptr_d(ptr %p, i64 %val) nounwind {
+; LA32-LABEL: stptr_d:
+; LA32:       # %bb.0:
+; LA32-NEXT:    ori $a3, $zero, 2052
+; LA32-NEXT:    add.w $a3, $a0, $a3
+; LA32-NEXT:    st.w $a2, $a3, 0
+; LA32-NEXT:    ori $a2, $zero, 2048
+; LA32-NEXT:    add.w $a0, $a0, $a2
+; LA32-NEXT:    st.w $a1, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: stptr_d:
+; LA64:       # %bb.0:
+; LA64-NEXT:    stptr.d $a1, $a0, 2048
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i64, ptr %p, i64 256
+  store i64 %val, ptr %addr, align 8
+  ret void
+}
+
+;; Check that stptr.d is not emitted for out-of-range offsets.
+define void @stptr_d_too_big_offset(ptr %p, i64 %val) nounwind {
+; LA32-LABEL: stptr_d_too_big_offset:
+; LA32:       # %bb.0:
+; LA32-NEXT:    lu12i.w $a3, 8
+; LA32-NEXT:    add.w $a4, $a0, $a3
+; LA32-NEXT:    st.w $a1, $a4, 0
+; LA32-NEXT:    ori $a1, $a3, 4
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    st.w $a2, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: stptr_d_too_big_offset:
+; LA64:       # %bb.0:
+; LA64-NEXT:    lu12i.w $a2, 8
+; LA64-NEXT:    stx.d $a1, $a0, $a2
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i64, ptr %p, i64 4096
+  store i64 %val, ptr %addr, align 8
+  ret void
+}