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[PowerPC] Fix infinite loop in peephole CR optimization (PR49509) 

If we encounter a degenerate select node where both operands are
the same, then we can continue negating the condition while swapping
operands, resulting in an infinite loop. Avoid this by bailing out
if both operands are the same.

Fixes https://bugs.llvm.org/show_bug.cgi?id=49509.

Differential Revision: https://reviews.llvm.org/D98340
This commit is contained in:
Nikita Popov 2021-03-10 14:37:09 +01:00
parent 8368e4d54c
commit 2489cbaa80
2 changed files with 87 additions and 0 deletions
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6
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -5937,7 +5937,13 @@ bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
User->getMachineOpcode() != PPC::SELECT_I8)
return false;
SDNode *Op1 = User->getOperand(1).getNode();
SDNode *Op2 = User->getOperand(2).getNode();
// If we have a degenerate select with two equal operands, swapping will
// not do anything, and we may run into an infinite loop.
if (Op1 == Op2)
return false;
if (!Op2->isMachineOpcode())
return false;

81
llvm/test/CodeGen/PowerPC/pr49509.ll Normal file
View File

@ -0,0 +1,81 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
target datalayout = "E-m:e-p:32:32-i64:64-n32"
define void @test() {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: bc 12, 20, .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb2
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: stw 3, 0(3)
; CHECK-NEXT: lis 3, 256
; CHECK-NEXT: stw 3, 0(3)
; CHECK-NEXT: blr
; CHECK-NEXT: .LBB0_2: # %bb1
; CHECK-NEXT: bclr 4, 20, 0
; CHECK-NEXT: # %bb.3: # %bb66
; CHECK-NEXT: lwz 4, 12(0)
; CHECK-NEXT: lwz 5, 8(0)
; CHECK-NEXT: lwz 6, 0(0)
; CHECK-NEXT: lwz 7, 4(0)
; CHECK-NEXT: lbz 3, 0(3)
; CHECK-NEXT: and 5, 5, 6
; CHECK-NEXT: and 4, 4, 7
; CHECK-NEXT: and 4, 4, 5
; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: lis 3, 256
; CHECK-NEXT: lis 7, 512
; CHECK-NEXT: bc 12, 2, .LBB0_4
; CHECK-NEXT: b .LBB0_5
; CHECK-NEXT: .LBB0_4: # %bb66
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: .LBB0_5: # %bb66
; CHECK-NEXT: cmpwi 1, 4, -1
; CHECK-NEXT: cmpwi 5, 4, -1
; CHECK-NEXT: li 6, 0
; CHECK-NEXT: bc 12, 6, .LBB0_6
; CHECK-NEXT: b .LBB0_7
; CHECK-NEXT: .LBB0_6: # %bb66
; CHECK-NEXT: addi 3, 7, 0
; CHECK-NEXT: .LBB0_7: # %bb66
; CHECK-NEXT: cror 20, 22, 2
; CHECK-NEXT: stw 3, 0(3)
; CHECK-NEXT: bc 12, 20, .LBB0_9
; CHECK-NEXT: # %bb.8: # %bb66
; CHECK-NEXT: ori 3, 6, 0
; CHECK-NEXT: b .LBB0_10
; CHECK-NEXT: .LBB0_9: # %bb66
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: .LBB0_10: # %bb66
; CHECK-NEXT: stw 3, 0(3)
; CHECK-NEXT: blr
bb:
br i1 undef, label %bb2, label %bb1
bb2: ; preds = %bb
%i = select i1 undef, i64 0, i64 72057594037927936
store i64 %i, i64* undef, align 8
ret void
bb1: ; preds = %bb
%i50 = load i8, i8* undef, align 8
%i52 = load i128, i128* null, align 8
%i62 = icmp eq i8 %i50, 0
br i1 undef, label %bb66, label %bb64
bb64: ; preds = %bb63
ret void
bb66: ; preds = %bb63
%i67 = lshr i128 -1, 0
%i68 = xor i128 %i52, -1
%i69 = add i128 0, %i68
%i70 = and i128 %i67, %i69
%i71 = icmp eq i128 %i70, 0
%i74 = select i1 %i62, i64 0, i64 72057594037927936
%i75 = select i1 %i71, i64 144115188075855872, i64 %i74
store i64 %i75, i64* undef, align 8
ret void
}