forked from OSchip/llvm-project
AMDGPU/GlobalISel: Add boilerplate for inline asm lowering
Test mostly from minor adjustments to the AArch64 one.
This commit is contained in:
Matt Arsenault
parent
6a4714030e
commit
2484109378
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@ -269,6 +269,7 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0) {
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MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(this);
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CallLoweringInfo.reset(new AMDGPUCallLowering(*getTargetLowering()));
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InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));
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Legalizer.reset(new AMDGPULegalizerInfo(*this, TM));
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RegBankInfo.reset(new AMDGPURegisterBankInfo(*this));
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InstSelector.reset(new AMDGPUInstructionSelector(
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@ -25,6 +25,7 @@
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#include "SIInstrInfo.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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@ -272,6 +273,7 @@ public:
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private:
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/// GlobalISel related APIs.
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std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
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std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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@ -421,6 +423,10 @@ public:
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return CallLoweringInfo.get();
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}
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const InlineAsmLowering *getInlineAsmLowering() const override {
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return InlineAsmLoweringInfo.get();
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}
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InstructionSelector *getInstructionSelector() const override {
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return InstSelector.get();
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}
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@ -0,0 +1,237 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
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define amdgpu_kernel void @asm_convergent() convergent{
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; CHECK-LABEL: name: asm_convergent
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: INLINEASM &s_barrier, 33 /* sideeffect isconvergent attdialect */, !0
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; CHECK: S_ENDPGM 0
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call void asm sideeffect "s_barrier", ""() convergent, !srcloc !0
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ret void
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}
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define amdgpu_kernel void @asm_simple_memory_clobber() {
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; CHECK-LABEL: name: asm_simple_memory_clobber
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, !0
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, !0
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; CHECK: S_ENDPGM 0
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call void asm sideeffect "", "~{memory}"(), !srcloc !0
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call void asm sideeffect "", ""(), !srcloc !0
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ret void
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}
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define amdgpu_kernel void @asm_simple_vgpr_clobber() {
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; CHECK-LABEL: name: asm_simple_vgpr_clobber
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: INLINEASM &"v_mov_b32 v0, 7", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $vgpr0, !0
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; CHECK: S_ENDPGM 0
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call void asm sideeffect "v_mov_b32 v0, 7", "~{v0}"(), !srcloc !0
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ret void
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}
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define amdgpu_kernel void @asm_simple_sgpr_clobber() {
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; CHECK-LABEL: name: asm_simple_sgpr_clobber
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: INLINEASM &"s_mov_b32 s0, 7", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $sgpr0, !0
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; CHECK: S_ENDPGM 0
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call void asm sideeffect "s_mov_b32 s0, 7", "~{s0}"(), !srcloc !0
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ret void
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}
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define amdgpu_kernel void @asm_simple_agpr_clobber() {
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; CHECK-LABEL: name: asm_simple_agpr_clobber
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: INLINEASM &"; def a0", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $agpr0, !0
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; CHECK: S_ENDPGM 0
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call void asm sideeffect "; def a0", "~{a0}"(), !srcloc !0
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ret void
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}
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define i32 @asm_vgpr_early_clobber() {
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; CHECK-LABEL: name: asm_vgpr_early_clobber
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: INLINEASM &"v_mov_b32 $0, 7; v_mov_b32 $1, 7", 1 /* sideeffect attdialect */, 1835019 /* regdef-ec:VGPR_32 */, def early-clobber %1, 1835019 /* regdef-ec:VGPR_32 */, def early-clobber %2, !0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %2
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; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY2]]
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; CHECK: $vgpr0 = COPY [[ADD]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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call { i32, i32 } asm sideeffect "v_mov_b32 $0, 7; v_mov_b32 $1, 7", "=&v,=&v"(), !srcloc !0
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%asmresult = extractvalue { i32, i32 } %1, 0
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%asmresult1 = extractvalue { i32, i32 } %1, 1
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%add = add i32 %asmresult, %asmresult1
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ret i32 %add
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}
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define i32 @test_specific_vgpr_output() nounwind {
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; CHECK-LABEL: name: test_specific_vgpr_output
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; CHECK: bb.1.entry:
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; CHECK: liveins: $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: INLINEASM &"v_mov_b32 v1, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: $vgpr0 = COPY [[COPY1]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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entry:
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%0 = tail call i32 asm "v_mov_b32 v1, 7", "={v1}"() nounwind
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ret i32 %0
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}
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define i32 @test_single_vgpr_output() nounwind {
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; CHECK-LABEL: name: test_single_vgpr_output
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; CHECK: bb.1.entry:
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; CHECK: liveins: $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: INLINEASM &"v_mov_b32 $0, 7", 0 /* attdialect */, 1835018 /* regdef:VGPR_32 */, def %1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
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; CHECK: $vgpr0 = COPY [[COPY1]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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entry:
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%0 = tail call i32 asm "v_mov_b32 $0, 7", "=v"() nounwind
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ret i32 %0
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}
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define i32 @test_single_sgpr_output_s32() nounwind {
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; CHECK-LABEL: name: test_single_sgpr_output_s32
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; CHECK: bb.1.entry:
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; CHECK: liveins: $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
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; CHECK: $vgpr0 = COPY [[COPY1]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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entry:
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%0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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ret i32 %0
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}
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; Check support for returning several floats
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define float @test_multiple_register_outputs_same() #0 {
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; CHECK-LABEL: name: test_multiple_register_outputs_same
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: INLINEASM &"v_mov_b32 $0, 0; v_mov_b32 $1, 1", 0 /* attdialect */, 1835018 /* regdef:VGPR_32 */, def %1, 1835018 /* regdef:VGPR_32 */, def %2
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %2
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; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY1]], [[COPY2]]
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; CHECK: $vgpr0 = COPY [[FADD]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%1 = call { float, float } asm "v_mov_b32 $0, 0; v_mov_b32 $1, 1", "=v,=v"()
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%asmresult = extractvalue { float, float } %1, 0
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%asmresult1 = extractvalue { float, float } %1, 1
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%add = fadd float %asmresult, %asmresult1
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ret float %add
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}
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; Check support for returning several floats
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define double @test_multiple_register_outputs_mixed() #0 {
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; CHECK-LABEL: name: test_multiple_register_outputs_mixed
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: INLINEASM &"v_mov_b32 $0, 0; v_add_f64 $1, 0, 0", 0 /* attdialect */, 1835018 /* regdef:VGPR_32 */, def %1, 2883594 /* regdef:VReg_64 */, def %2
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %2
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
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; CHECK: $vgpr0 = COPY [[UV]](s32)
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; CHECK: $vgpr1 = COPY [[UV1]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0, implicit $vgpr1
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%1 = call { float, double } asm "v_mov_b32 $0, 0; v_add_f64 $1, 0, 0", "=v,=v"()
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%asmresult = extractvalue { float, double } %1, 1
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ret double %asmresult
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}
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define float @test_vector_output() nounwind {
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; CHECK-LABEL: name: test_vector_output
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: INLINEASM &"v_add_f64 $0, 0, 0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vgpr14_vgpr15
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr14_vgpr15
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; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY1]](<2 x s32>), [[C]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%1 = tail call <2 x float> asm sideeffect "v_add_f64 $0, 0, 0", "={v[14:15]}"() nounwind
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%2 = extractelement <2 x float> %1, i32 0
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ret float %2
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}
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define amdgpu_kernel void @test_input_vgpr_imm() {
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; CHECK-LABEL: name: test_input_vgpr_imm
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[C]](s32)
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; CHECK: INLINEASM &"v_mov_b32 v0, $0", 1 /* sideeffect attdialect */, 9 /* reguse */, [[COPY]]
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; CHECK: S_ENDPGM 0
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call void asm sideeffect "v_mov_b32 v0, $0", "v"(i32 42)
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ret void
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}
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define amdgpu_kernel void @test_input_sgpr_imm() {
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; CHECK-LABEL: name: test_input_sgpr_imm
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
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; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY [[C]](s32)
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; CHECK: INLINEASM &"s_mov_b32 s0, $0", 1 /* sideeffect attdialect */, 9 /* reguse */, [[COPY]]
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; CHECK: S_ENDPGM 0
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call void asm sideeffect "s_mov_b32 s0, $0", "s"(i32 42)
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ret void
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}
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define amdgpu_kernel void @test_input_imm() {
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; CHECK-LABEL: name: test_input_imm
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: INLINEASM &"s_mov_b32 s0, $0", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42
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; CHECK: INLINEASM &"s_mov_b64 s[0:1], $0", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42
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; CHECK: S_ENDPGM 0
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call void asm sideeffect "s_mov_b32 s0, $0", "i"(i32 42)
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call void asm sideeffect "s_mov_b64 s[0:1], $0", "i"(i64 42)
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ret void
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}
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define float @test_input_vgpr(i32 %src) nounwind {
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; CHECK-LABEL: name: test_input_vgpr
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; CHECK: bb.1.entry:
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)
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; CHECK: INLINEASM &"v_add_f32 $0, 1.0, $1", 0 /* attdialect */, 1835018 /* regdef:VGPR_32 */, def %2, 9 /* reguse */, [[COPY2]]
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY %2
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; CHECK: $vgpr0 = COPY [[COPY3]](s32)
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; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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entry:
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%0 = tail call float asm "v_add_f32 $0, 1.0, $1", "=v,v"(i32 %src) nounwind
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ret float %0
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}
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define i32 @test_memory_constraint(i32 addrspace(3)* %a) nounwind {
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; CHECK-LABEL: name: test_memory_constraint
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: INLINEASM &"ds_read_b32 $0, $1", 8 /* mayload attdialect */, 1835018 /* regdef:VGPR_32 */, def %2, 196622 /* mem:m */, [[COPY]](p3)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %2
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; CHECK: $vgpr0 = COPY [[COPY2]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%1 = tail call i32 asm "ds_read_b32 $0, $1", "=v,*m"(i32 addrspace(3)* %a)
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ret i32 %1
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}
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!0 = !{i32 70}
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