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Continue the SimpleValueType-ification. 

llvm-svn: 78593
This commit is contained in:
Owen Anderson 2009-08-10 20:18:46 +00:00
parent a1025faf84
commit 246617857f
5 changed files with 29 additions and 31 deletions
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6
llvm/include/llvm/Target/TargetLowering.h
View File

@ -944,11 +944,9 @@ protected:
/// setOperationAction - Indicate that the specified operation does not work
/// with the specified type and indicate what to do about it.
void setOperationAction(unsigned Op, MVT VT,
void setOperationAction(unsigned Op, MVT::SimpleValueType VT,
LegalizeAction Action) {
assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 &&
Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
unsigned I = (unsigned) VT.getSimpleVT();
unsigned I = (unsigned)VT;
unsigned J = I & 31;
I = I >> 5;
OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));

28
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -61,35 +61,35 @@ static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
MVT PromotedBitwiseVT) {
if (VT != PromotedLdStVT) {
setOperationAction(ISD::LOAD, VT, Promote);
setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
setOperationAction(ISD::STORE, VT, Promote);
setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
}
MVT ElemTy = VT.getVectorElementType();
if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
setOperationAction(ISD::VSETCC, VT, Custom);
setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(), Custom);
setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
if (VT.isInteger()) {
setOperationAction(ISD::SHL, VT, Custom);
setOperationAction(ISD::SRA, VT, Custom);
setOperationAction(ISD::SRL, VT, Custom);
setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
}
// Promote all bit-wise operations.
if (VT.isInteger() && VT != PromotedBitwiseVT) {
setOperationAction(ISD::AND, VT, Promote);
setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
setOperationAction(ISD::OR, VT, Promote);
setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
setOperationAction(ISD::XOR, VT, Promote);
setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
}
}

8
llvm/lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -168,7 +168,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
// SPU's loads and stores have to be custom lowered:
for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::i128;
++sctype) {
MVT VT = (MVT::SimpleValueType)sctype;
MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom);
@ -184,7 +184,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
for (unsigned sctype = (unsigned) MVT::f32; sctype < (unsigned) MVT::f64;
++sctype) {
MVT VT = (MVT::SimpleValueType) sctype;
MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype;
setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom);
@ -391,7 +391,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
// appropriate instructions to materialize the address.
for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128;
++sctype) {
MVT VT = (MVT::SimpleValueType)sctype;
MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
setOperationAction(ISD::GlobalAddress, VT, Custom);
setOperationAction(ISD::ConstantPool, VT, Custom);
@ -434,7 +434,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
MVT VT = (MVT::SimpleValueType)i;
MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD, VT, Legal);

2
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -283,7 +283,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
// will selectively turn on ones that can be effectively codegen'd.
for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
MVT VT = (MVT::SimpleValueType)i;
MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD , VT, Legal);

16
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -723,9 +723,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// Do not attempt to custom lower non-128-bit vectors
if (!VT.is128BitVector())
continue;
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
}
setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
@ -748,15 +748,15 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
if (!VT.is128BitVector()) {
continue;
}
setOperationAction(ISD::AND, VT, Promote);
setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::AND, VT, MVT::v2i64);
setOperationAction(ISD::OR, VT, Promote);
setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::OR, VT, MVT::v2i64);
setOperationAction(ISD::XOR, VT, Promote);
setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
setOperationAction(ISD::LOAD, VT, Promote);
setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
setOperationAction(ISD::SELECT, VT, Promote);
setOperationAction(ISD::SELECT, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
}