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[Mips][Codegen] Fix fast-isel mixing of FGR64 and AFGR64 registers 

Fast-isel was picking AFGR64 register class for processing call
arguments when +fp64 options was used. We simply check is option +fp64
is used and pick appropriate register.

Patch by Mirko Brkusanin.

Differential Revision: https://reviews.llvm.org/D65886

llvm-svn: 368433
This commit is contained in:
Simon Atanasyan 2019-08-09 12:02:32 +00:00
parent cbec9af6bf
commit 242c5a70d4
2 changed files with 37 additions and 2 deletions
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10
llvm/lib/Target/Mips/MipsFastISel.cpp
View File

@ -1162,14 +1162,20 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
if (ArgVT == MVT::f32) {
VA.convertToReg(Mips::F12);
} else if (ArgVT == MVT::f64) {
VA.convertToReg(Mips::D6);
if (Subtarget->isFP64bit())
VA.convertToReg(Mips::D6_64);
else
VA.convertToReg(Mips::D6);
}
} else if (i == 1) {
if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
if (ArgVT == MVT::f32) {
VA.convertToReg(Mips::F14);
} else if (ArgVT == MVT::f64) {
VA.convertToReg(Mips::D7);
if (Subtarget->isFP64bit())
VA.convertToReg(Mips::D7_64);
else
VA.convertToReg(Mips::D7);
}
}
}

29
llvm/test/CodeGen/Mips/copy-fp64.ll Normal file
View File

@ -0,0 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -march=mips -mcpu=mips32r2 -O0 -relocation-model=pic -mattr=+fp64 \
; RUN: -stop-before=prologepilog %s -o - | FileCheck %s
declare double @bar(double)
define double @foo(double %self) {
; CHECK-LABEL: name: foo
; CHECK: bb.0.start:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $d12_64, $t9, $v0
; CHECK: renamable $at = ADDu killed $v0, killed $t9
; CHECK: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; CHECK: $d6_64 = COPY killed renamable $d12_64
; CHECK: renamable $t9 = LW killed renamable $at, target-flags(mips-got) @bar
; CHECK: dead $ra = JALR killed $t9, csr_o32_fp64, target-flags(mips-jalr) <mcsymbol bar>, implicit-def dead $ra, implicit killed $d6_64, implicit-def $d0_64
; CHECK: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; CHECK: SDC164 killed $d0_64, %stack.0, 0 :: (store 8 into %stack.0)
; CHECK: bb.1.bb1:
; CHECK: $d0_64 = LDC164 %stack.0, 0 :: (load 8 from %stack.0)
; CHECK: RetRA implicit killed $d0_64
start:
%0 = call double @bar(double %self)
br label %bb1
bb1:
ret double %0
}