forked from OSchip/llvm-project
[X86] Apply the Update LLC Test Checks tool on the rotate tests.
Also added cases demonstrating pr30644. llvm-svn: 283667
This commit is contained in:
Zvi Rackover
parent
d0d90fb9b2
commit
2413d475fc
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@ -1,7 +1,13 @@
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; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
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; RUN: grep "ro[rl]" | count 12
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux -march=x86 | FileCheck %s
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define i32 @rotl32(i32 %A, i8 %Amt) {
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; CHECK-LABEL: rotl32:
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; CHECK: # BB#0:
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: roll %cl, %eax
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; CHECK-NEXT: retl
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%shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
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%B = shl i32 %A, %shift.upgrd.1 ; <i32> [#uses=1]
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%Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
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@ -12,6 +18,12 @@ define i32 @rotl32(i32 %A, i8 %Amt) {
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}
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define i32 @rotr32(i32 %A, i8 %Amt) {
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; CHECK-LABEL: rotr32:
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; CHECK: # BB#0:
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: rorl %cl, %eax
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; CHECK-NEXT: retl
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%shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
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%B = lshr i32 %A, %shift.upgrd.3 ; <i32> [#uses=1]
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%Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
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@ -22,6 +34,11 @@ define i32 @rotr32(i32 %A, i8 %Amt) {
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}
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define i32 @rotli32(i32 %A) {
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; CHECK-LABEL: rotli32:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: roll $5, %eax
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; CHECK-NEXT: retl
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%B = shl i32 %A, 5 ; <i32> [#uses=1]
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%C = lshr i32 %A, 27 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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@ -29,13 +46,48 @@ define i32 @rotli32(i32 %A) {
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}
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define i32 @rotri32(i32 %A) {
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; CHECK-LABEL: rotri32:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: roll $27, %eax
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; CHECK-NEXT: retl
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%B = lshr i32 %A, 5 ; <i32> [#uses=1]
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%C = shl i32 %A, 27 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotl1_32(i32 %A) {
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; CHECK-LABEL: rotl1_32:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: roll %eax
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; CHECK-NEXT: retl
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%B = shl i32 %A, 1 ; <i32> [#uses=1]
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%C = lshr i32 %A, 31 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotr1_32(i32 %A) {
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; CHECK-LABEL: rotr1_32:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: roll $31, %eax
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; CHECK-NEXT: retl
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%B = shl i32 %A, 31 ; <i32> [#uses=1]
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%C = lshr i32 %A, 1 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i16 @rotl16(i16 %A, i8 %Amt) {
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; CHECK-LABEL: rotl16:
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; CHECK: # BB#0:
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
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; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: rolw %cl, %ax
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; CHECK-NEXT: retl
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%shift.upgrd.5 = zext i8 %Amt to i16 ; <i16> [#uses=1]
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%B = shl i16 %A, %shift.upgrd.5 ; <i16> [#uses=1]
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%Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
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@ -46,6 +98,12 @@ define i16 @rotl16(i16 %A, i8 %Amt) {
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}
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define i16 @rotr16(i16 %A, i8 %Amt) {
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; CHECK-LABEL: rotr16:
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; CHECK: # BB#0:
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
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; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: rorw %cl, %ax
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; CHECK-NEXT: retl
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%shift.upgrd.7 = zext i8 %Amt to i16 ; <i16> [#uses=1]
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%B = lshr i16 %A, %shift.upgrd.7 ; <i16> [#uses=1]
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%Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
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@ -56,6 +114,11 @@ define i16 @rotr16(i16 %A, i8 %Amt) {
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}
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define i16 @rotli16(i16 %A) {
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; CHECK-LABEL: rotli16:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: rolw $5, %ax
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; CHECK-NEXT: retl
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%B = shl i16 %A, 5 ; <i16> [#uses=1]
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%C = lshr i16 %A, 11 ; <i16> [#uses=1]
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%D = or i16 %B, %C ; <i16> [#uses=1]
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@ -63,13 +126,48 @@ define i16 @rotli16(i16 %A) {
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}
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define i16 @rotri16(i16 %A) {
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; CHECK-LABEL: rotri16:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: rolw $11, %ax
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; CHECK-NEXT: retl
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%B = lshr i16 %A, 5 ; <i16> [#uses=1]
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%C = shl i16 %A, 11 ; <i16> [#uses=1]
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%D = or i16 %B, %C ; <i16> [#uses=1]
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ret i16 %D
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}
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define i16 @rotl1_16(i16 %A) {
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; CHECK-LABEL: rotl1_16:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: rolw %ax
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; CHECK-NEXT: retl
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%B = shl i16 %A, 1 ; <i16> [#uses=1]
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%C = lshr i16 %A, 15 ; <i16> [#uses=1]
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%D = or i16 %B, %C ; <i16> [#uses=1]
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ret i16 %D
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}
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define i16 @rotr1_16(i16 %A) {
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; CHECK-LABEL: rotr1_16:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: rolw $15, %ax
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; CHECK-NEXT: retl
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%B = lshr i16 %A, 1 ; <i16> [#uses=1]
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%C = shl i16 %A, 15 ; <i16> [#uses=1]
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%D = or i16 %B, %C ; <i16> [#uses=1]
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ret i16 %D
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}
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define i8 @rotl8(i8 %A, i8 %Amt) {
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; CHECK-LABEL: rotl8:
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; CHECK: # BB#0:
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK-NEXT: rolb %cl, %al
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; CHECK-NEXT: retl
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%B = shl i8 %A, %Amt ; <i8> [#uses=1]
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%Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
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%C = lshr i8 %A, %Amt2 ; <i8> [#uses=1]
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@ -78,6 +176,12 @@ define i8 @rotl8(i8 %A, i8 %Amt) {
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}
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define i8 @rotr8(i8 %A, i8 %Amt) {
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; CHECK-LABEL: rotr8:
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; CHECK: # BB#0:
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK-NEXT: rorb %cl, %al
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; CHECK-NEXT: retl
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%B = lshr i8 %A, %Amt ; <i8> [#uses=1]
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%Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
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%C = shl i8 %A, %Amt2 ; <i8> [#uses=1]
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@ -86,6 +190,11 @@ define i8 @rotr8(i8 %A, i8 %Amt) {
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}
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define i8 @rotli8(i8 %A) {
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; CHECK-LABEL: rotli8:
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; CHECK: # BB#0:
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK-NEXT: rolb $5, %al
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; CHECK-NEXT: retl
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%B = shl i8 %A, 5 ; <i8> [#uses=1]
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%C = lshr i8 %A, 3 ; <i8> [#uses=1]
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%D = or i8 %B, %C ; <i8> [#uses=1]
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@ -93,8 +202,37 @@ define i8 @rotli8(i8 %A) {
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}
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define i8 @rotri8(i8 %A) {
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; CHECK-LABEL: rotri8:
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; CHECK: # BB#0:
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK-NEXT: rolb $3, %al
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; CHECK-NEXT: retl
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%B = lshr i8 %A, 5 ; <i8> [#uses=1]
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%C = shl i8 %A, 3 ; <i8> [#uses=1]
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%D = or i8 %B, %C ; <i8> [#uses=1]
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ret i8 %D
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}
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define i8 @rotl1_8(i8 %A) {
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; CHECK-LABEL: rotl1_8:
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; CHECK: # BB#0:
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK-NEXT: rolb %al
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; CHECK-NEXT: retl
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%B = shl i8 %A, 1 ; <i8> [#uses=1]
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%C = lshr i8 %A, 7 ; <i8> [#uses=1]
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%D = or i8 %B, %C ; <i8> [#uses=1]
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ret i8 %D
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}
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define i8 @rotr1_8(i8 %A) {
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; CHECK-LABEL: rotr1_8:
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; CHECK: # BB#0:
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; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al
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; CHECK-NEXT: rolb $7, %al
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; CHECK-NEXT: retl
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%B = lshr i8 %A, 1 ; <i8> [#uses=1]
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%C = shl i8 %A, 7 ; <i8> [#uses=1]
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%D = or i8 %B, %C ; <i8> [#uses=1]
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ret i8 %D
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}
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