forked from OSchip/llvm-project
[Hexagon] Fix building 64-bit vector from constant values
The constants were aggregated in a reverse order. llvm-svn: 322303
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@ -2652,7 +2652,7 @@ HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
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uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull
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uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull
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: (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
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: (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
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for (unsigned i = 0; i != Num; ++i)
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for (unsigned i = 0; i != Num; ++i)
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Val = (Val << W) | (Consts[i]->getZExtValue() & Mask);
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Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
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SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
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SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
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return DAG.getBitcast(VecTy, V0);
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return DAG.getBitcast(VecTy, V0);
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}
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}
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@ -0,0 +1,8 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that the value produced is 0x0706050403020100.
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; CHECK: r1:0 = CONST64(#506097522914230528)
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define <8 x i8> @fred() {
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ret <8 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>
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}
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