forked from OSchip/llvm-project
parent
a7bb16ad86
commit
23f1f957d5
llvm/include/llvm/MC
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@ -230,7 +230,7 @@ public:
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friend class MCRegUnitIterator;
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friend class MCRegUnitIterator;
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friend class MCRegUnitRootIterator;
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friend class MCRegUnitRootIterator;
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/// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
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/// \brief Initialize MCRegisterInfo, called by TableGen
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/// auto-generated routines. *DO NOT USE*.
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/// auto-generated routines. *DO NOT USE*.
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void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
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void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
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unsigned PC,
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unsigned PC,
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@ -257,7 +257,7 @@ public:
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RegEncodingTable = RET;
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RegEncodingTable = RET;
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}
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}
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/// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf
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/// \brief Used to initialize LLVM register to Dwarf
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/// register number mapping. Called by TableGen auto-generated routines.
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/// register number mapping. Called by TableGen auto-generated routines.
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/// *DO NOT USE*.
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/// *DO NOT USE*.
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void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
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void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
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@ -271,7 +271,7 @@ public:
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}
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}
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}
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}
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/// mapDwarfRegsToLLVMRegs - Used to initialize Dwarf register to LLVM
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/// \brief Used to initialize Dwarf register to LLVM
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/// register number mapping. Called by TableGen auto-generated routines.
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/// register number mapping. Called by TableGen auto-generated routines.
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/// *DO NOT USE*.
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/// *DO NOT USE*.
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void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
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void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
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@ -294,7 +294,7 @@ public:
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L2SEHRegs[LLVMReg] = SEHReg;
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L2SEHRegs[LLVMReg] = SEHReg;
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}
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}
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/// getRARegister - This method should return the register where the return
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/// \brief This method should return the register where the return
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/// address can be found.
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/// address can be found.
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unsigned getRARegister() const {
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unsigned getRARegister() const {
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return RAReg;
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return RAReg;
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@ -311,65 +311,63 @@ public:
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return Desc[RegNo];
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return Desc[RegNo];
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}
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}
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/// Provide a get method, equivalent to [], but more useful if we have a
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/// \brief Provide a get method, equivalent to [], but more useful with a
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/// pointer to this object.
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/// pointer to this object.
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///
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const MCRegisterDesc &get(unsigned RegNo) const {
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const MCRegisterDesc &get(unsigned RegNo) const {
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return operator[](RegNo);
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return operator[](RegNo);
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}
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}
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/// getSubReg - Returns the physical register number of sub-register "Index"
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/// \brief Returns the physical register number of sub-register "Index"
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/// for physical register RegNo. Return zero if the sub-register does not
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/// for physical register RegNo. Return zero if the sub-register does not
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/// exist.
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/// exist.
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unsigned getSubReg(unsigned Reg, unsigned Idx) const;
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unsigned getSubReg(unsigned Reg, unsigned Idx) const;
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/// getMatchingSuperReg - Return a super-register of the specified register
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/// \brief Return a super-register of the specified register
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/// Reg so its sub-register of index SubIdx is Reg.
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/// Reg so its sub-register of index SubIdx is Reg.
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unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
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unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
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const MCRegisterClass *RC) const;
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const MCRegisterClass *RC) const;
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/// getSubRegIndex - For a given register pair, return the sub-register index
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/// \brief For a given register pair, return the sub-register index
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/// if the second register is a sub-register of the first. Return zero
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/// if the second register is a sub-register of the first. Return zero
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/// otherwise.
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/// otherwise.
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unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
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unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
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/// getName - Return the human-readable symbolic target-specific name for the
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/// \brief Return the human-readable symbolic target-specific name for the
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/// specified physical register.
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/// specified physical register.
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const char *getName(unsigned RegNo) const {
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const char *getName(unsigned RegNo) const {
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return RegStrings + get(RegNo).Name;
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return RegStrings + get(RegNo).Name;
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}
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}
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/// getNumRegs - Return the number of registers this target has (useful for
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/// \brief Return the number of registers this target has (useful for
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/// sizing arrays holding per register information)
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/// sizing arrays holding per register information)
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unsigned getNumRegs() const {
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unsigned getNumRegs() const {
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return NumRegs;
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return NumRegs;
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}
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}
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/// getNumSubRegIndices - Return the number of sub-register indices
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/// \brief Return the number of sub-register indices
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/// understood by the target. Index 0 is reserved for the no-op sub-register,
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/// understood by the target. Index 0 is reserved for the no-op sub-register,
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/// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
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/// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
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unsigned getNumSubRegIndices() const {
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unsigned getNumSubRegIndices() const {
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return NumSubRegIndices;
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return NumSubRegIndices;
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}
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}
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/// getNumRegUnits - Return the number of (native) register units in the
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/// \brief Return the number of (native) register units in the
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/// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
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/// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
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/// can be accessed through MCRegUnitIterator defined below.
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/// can be accessed through MCRegUnitIterator defined below.
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unsigned getNumRegUnits() const {
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unsigned getNumRegUnits() const {
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return NumRegUnits;
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return NumRegUnits;
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}
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}
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/// getDwarfRegNum - Map a target register to an equivalent dwarf register
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/// \brief Map a target register to an equivalent dwarf register
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/// number. Returns -1 if there is no equivalent value. The second
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/// number. Returns -1 if there is no equivalent value. The second
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/// parameter allows targets to use different numberings for EH info and
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/// parameter allows targets to use different numberings for EH info and
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/// debugging info.
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/// debugging info.
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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/// getLLVMRegNum - Map a dwarf register back to a target register.
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/// \brief Map a dwarf register back to a target register.
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///
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int getLLVMRegNum(unsigned RegNum, bool isEH) const;
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int getLLVMRegNum(unsigned RegNum, bool isEH) const;
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/// getSEHRegNum - Map a target register to an equivalent SEH register
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/// \brief Map a target register to an equivalent SEH register
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/// number. Returns LLVM register number if there is no equivalent value.
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/// number. Returns LLVM register number if there is no equivalent value.
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int getSEHRegNum(unsigned RegNum) const;
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int getSEHRegNum(unsigned RegNum) const;
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@ -380,34 +378,35 @@ public:
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return (unsigned)(regclass_end()-regclass_begin());
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return (unsigned)(regclass_end()-regclass_begin());
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}
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}
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/// getRegClass - Returns the register class associated with the enumeration
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/// \brief Returns the register class associated with the enumeration
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/// value. See class MCOperandInfo.
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/// value. See class MCOperandInfo.
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const MCRegisterClass& getRegClass(unsigned i) const {
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const MCRegisterClass& getRegClass(unsigned i) const {
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assert(i < getNumRegClasses() && "Register Class ID out of range");
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assert(i < getNumRegClasses() && "Register Class ID out of range");
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return Classes[i];
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return Classes[i];
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}
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}
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/// getEncodingValue - Returns the encoding for RegNo
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/// \brief Returns the encoding for RegNo
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uint16_t getEncodingValue(unsigned RegNo) const {
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uint16_t getEncodingValue(unsigned RegNo) const {
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assert(RegNo < NumRegs &&
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assert(RegNo < NumRegs &&
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"Attempting to get encoding for invalid register number!");
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"Attempting to get encoding for invalid register number!");
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return RegEncodingTable[RegNo];
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return RegEncodingTable[RegNo];
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}
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}
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/// Returns true if RegB is a sub-register of RegA.
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/// \brief Returns true if RegB is a sub-register of RegA.
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bool isSubRegister(unsigned RegA, unsigned RegB) const {
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bool isSubRegister(unsigned RegA, unsigned RegB) const {
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return isSuperRegister(RegB, RegA);
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return isSuperRegister(RegB, RegA);
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}
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}
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/// Returns true if RegB is a super-register of RegA.
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/// \brief Returns true if RegB is a super-register of RegA.
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bool isSuperRegister(unsigned RegA, unsigned RegB) const;
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bool isSuperRegister(unsigned RegA, unsigned RegB) const;
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/// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
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/// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA.
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bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
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bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
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return isSuperRegisterEq(RegB, RegA);
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return isSuperRegisterEq(RegB, RegA);
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}
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}
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/// Returns true if RegB is a super-register of RegA or if RegB == RegA.
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/// \brief Returns true if RegB is a super-register of RegA or if
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/// RegB == RegA.
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bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
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bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
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return RegA == RegB || isSuperRegister(RegA, RegB);
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return RegA == RegB || isSuperRegister(RegA, RegB);
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}
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}
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@ -519,17 +518,17 @@ public:
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Reg1 = MCRI->RegUnitRoots[RegUnit][1];
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Reg1 = MCRI->RegUnitRoots[RegUnit][1];
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}
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}
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/// Dereference to get the current root register.
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/// \brief Dereference to get the current root register.
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unsigned operator*() const {
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unsigned operator*() const {
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return Reg0;
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return Reg0;
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}
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}
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/// isValid - Check if the iterator is at the end of the list.
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/// \brief Check if the iterator is at the end of the list.
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bool isValid() const {
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bool isValid() const {
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return Reg0;
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return Reg0;
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}
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}
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/// Preincrement to move to the next root register.
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/// \brief Preincrement to move to the next root register.
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void operator++() {
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void operator++() {
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assert(isValid() && "Cannot move off the end of the list.");
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assert(isValid() && "Cannot move off the end of the list.");
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Reg0 = Reg1;
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Reg0 = Reg1;
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