forked from OSchip/llvm-project
Remove the X86PeepholeOptimizerPass, a truly horrible old hack that is now
obsolete. yaay :) llvm-svn: 25939
This commit is contained in:
Chris Lattner
parent
c408558638
commit
23d55f2547
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@ -38,11 +38,6 @@ FunctionPass *createX86ISelPattern(TargetMachine &TM);
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///
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FunctionPass *createX86ISelDag(TargetMachine &TM);
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/// createX86PeepholeOptimizer - Create a pass to perform X86 specific peephole
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/// optimizations.
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///
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FunctionPass *createX86PeepholeOptimizerPass();
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/// createX86FloatingPointStackifierPass - This function returns a pass which
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/// converts floating point register references and pseudo instructions into
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/// floating point stack references and physical instructions.
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@ -1,178 +0,0 @@
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//===-- X86PeepholeOpt.cpp - X86 Peephole Optimizer -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains an immediate shrinker for the X86. FIXME: Remove when
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// the dag isel makes this obsolete!
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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namespace {
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Statistic<> NumPHOpts("x86-peephole",
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"Number of peephole optimization performed");
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Statistic<> NumPHMoves("x86-peephole", "Number of peephole moves folded");
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struct PH : public MachineFunctionPass {
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virtual bool runOnMachineFunction(MachineFunction &MF);
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bool PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I);
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virtual const char *getPassName() const { return "X86 Peephole Optimizer"; }
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};
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}
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FunctionPass *llvm::createX86PeepholeOptimizerPass() { return new PH(); }
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bool PH::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
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if (PeepholeOptimize(*BI, I)) {
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Changed = true;
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++NumPHOpts;
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} else
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++I;
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return Changed;
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}
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bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I) {
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assert(I != MBB.end());
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MachineBasicBlock::iterator NextI = next(I);
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MachineInstr *MI = I;
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MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
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unsigned Size = 0;
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switch (MI->getOpcode()) {
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// A large number of X86 instructions have forms which take an 8-bit
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// immediate despite the fact that the operands are 16 or 32 bits. Because
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// this can save three bytes of code size (and icache space), we want to
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// shrink them if possible.
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case X86::IMUL16rri: case X86::IMUL32rri:
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assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
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if (MI->getOperand(2).isImmediate()) {
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int Val = MI->getOperand(2).getImmedValue();
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// If the value is the same when signed extended from 8 bits...
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if (Val == (signed int)(signed char)Val) {
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unsigned Opcode;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown opcode value!");
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case X86::IMUL16rri: Opcode = X86::IMUL16rri8; break;
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case X86::IMUL32rri: Opcode = X86::IMUL32rri8; break;
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}
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unsigned R0 = MI->getOperand(0).getReg();
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unsigned R1 = MI->getOperand(1).getReg();
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I = MBB.insert(MBB.erase(I),
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BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val));
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return true;
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}
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}
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return false;
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case X86::ADD16ri: case X86::ADD32ri: case X86::ADC32ri:
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case X86::SUB16ri: case X86::SUB32ri:
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case X86::SBB16ri: case X86::SBB32ri:
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case X86::AND16ri: case X86::AND32ri:
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case X86::OR16ri: case X86::OR32ri:
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case X86::XOR16ri: case X86::XOR32ri:
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assert(MI->getNumOperands() == 2 && "These should all have 2 operands!");
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if (MI->getOperand(1).isImmediate()) {
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int Val = MI->getOperand(1).getImmedValue();
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// If the value is the same when signed extended from 8 bits...
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if (Val == (signed int)(signed char)Val) {
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unsigned Opcode;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown opcode value!");
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case X86::ADD16ri: Opcode = X86::ADD16ri8; break;
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case X86::ADD32ri: Opcode = X86::ADD32ri8; break;
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case X86::ADC32ri: Opcode = X86::ADC32ri8; break;
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case X86::SUB16ri: Opcode = X86::SUB16ri8; break;
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case X86::SUB32ri: Opcode = X86::SUB32ri8; break;
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case X86::SBB16ri: Opcode = X86::SBB16ri8; break;
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case X86::SBB32ri: Opcode = X86::SBB32ri8; break;
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case X86::AND16ri: Opcode = X86::AND16ri8; break;
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case X86::AND32ri: Opcode = X86::AND32ri8; break;
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case X86::OR16ri: Opcode = X86::OR16ri8; break;
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case X86::OR32ri: Opcode = X86::OR32ri8; break;
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case X86::XOR16ri: Opcode = X86::XOR16ri8; break;
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case X86::XOR32ri: Opcode = X86::XOR32ri8; break;
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}
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unsigned R0 = MI->getOperand(0).getReg();
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I = MBB.insert(MBB.erase(I),
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BuildMI(Opcode, 1, R0, MachineOperand::UseAndDef)
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.addZImm((char)Val));
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return true;
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}
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}
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return false;
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case X86::ADD16mi: case X86::ADD32mi: case X86::ADC32mi:
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case X86::SUB16mi: case X86::SUB32mi:
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case X86::SBB16mi: case X86::SBB32mi:
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case X86::AND16mi: case X86::AND32mi:
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case X86::OR16mi: case X86::OR32mi:
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case X86::XOR16mi: case X86::XOR32mi:
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assert(MI->getNumOperands() == 5 && "These should all have 5 operands!");
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if (MI->getOperand(4).isImmediate()) {
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int Val = MI->getOperand(4).getImmedValue();
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// If the value is the same when signed extended from 8 bits...
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if (Val == (signed int)(signed char)Val) {
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unsigned Opcode;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown opcode value!");
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case X86::ADD16mi: Opcode = X86::ADD16mi8; break;
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case X86::ADD32mi: Opcode = X86::ADD32mi8; break;
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case X86::ADC32mi: Opcode = X86::ADC32mi8; break;
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case X86::SUB16mi: Opcode = X86::SUB16mi8; break;
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case X86::SUB32mi: Opcode = X86::SUB32mi8; break;
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case X86::SBB16mi: Opcode = X86::SBB16mi8; break;
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case X86::SBB32mi: Opcode = X86::SBB32mi8; break;
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case X86::AND16mi: Opcode = X86::AND16mi8; break;
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case X86::AND32mi: Opcode = X86::AND32mi8; break;
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case X86::OR16mi: Opcode = X86::OR16mi8; break;
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case X86::OR32mi: Opcode = X86::OR32mi8; break;
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case X86::XOR16mi: Opcode = X86::XOR16mi8; break;
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case X86::XOR32mi: Opcode = X86::XOR32mi8; break;
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}
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unsigned R0 = MI->getOperand(0).getReg();
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unsigned Scale = MI->getOperand(1).getImmedValue();
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unsigned R1 = MI->getOperand(2).getReg();
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if (MI->getOperand(3).isImmediate()) {
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unsigned Offset = MI->getOperand(3).getImmedValue();
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I = MBB.insert(MBB.erase(I),
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BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
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addReg(R1).addSImm(Offset).addZImm((char)Val));
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} else if (MI->getOperand(3).isGlobalAddress()) {
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GlobalValue *GA = MI->getOperand(3).getGlobal();
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int Offset = MI->getOperand(3).getOffset();
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I = MBB.insert(MBB.erase(I),
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BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
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addReg(R1).addGlobalAddress(GA, false, Offset).
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addZImm((char)Val));
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}
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return true;
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}
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}
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return false;
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default:
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return false;
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}
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}
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@ -129,8 +129,6 @@ bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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PM.add(createX86PeepholeOptimizerPass());
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if (PrintMachineCode) // Print the register-allocated code
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PM.add(createX86CodePrinterPass(std::cerr, *this));
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@ -198,8 +196,6 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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PM.add(createX86PeepholeOptimizerPass());
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if (PrintMachineCode) // Print the register-allocated code
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PM.add(createX86CodePrinterPass(std::cerr, TM));
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}
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