forked from OSchip/llvm-project
[FastISel][X86] Implement the FastLowerCall hook.
This implements the FastLowerCall hook, which is based on the DoSelectCall function. The implementation is very similar, but the target-independent call lowering part has been factored out. This should also enable patchpoint intrinsic lowering for FastISel on X86. Related to <rdar://problem/17427052>. llvm-svn: 213049
This commit is contained in:
Juergen Ributzka
parent
5ee9d90248
commit
23d43318c7
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@ -74,6 +74,7 @@ public:
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const LoadInst *LI) override;
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bool FastLowerArguments() override;
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bool FastLowerCall(CallLoweringInfo &CLI) override;
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#include "X86GenFastISel.inc"
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@ -2654,18 +2655,19 @@ bool X86FastISel::X86SelectCall(const Instruction *I) {
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return DoSelectCall(I, nullptr);
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}
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static unsigned computeBytesPoppedByCallee(const X86Subtarget &Subtarget,
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const ImmutableCallSite &CS) {
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if (Subtarget.is64Bit())
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static unsigned computeBytesPoppedByCallee(const X86Subtarget *Subtarget,
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CallingConv::ID CC,
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ImmutableCallSite *CS) {
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if (Subtarget->is64Bit())
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return 0;
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if (Subtarget.getTargetTriple().isOSMSVCRT())
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if (Subtarget->getTargetTriple().isOSMSVCRT())
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return 0;
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CallingConv::ID CC = CS.getCallingConv();
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if (CC == CallingConv::Fast || CC == CallingConv::GHC)
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if (CC == CallingConv::Fast || CC == CallingConv::GHC ||
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CC == CallingConv::HiPE)
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return 0;
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if (!CS.paramHasAttr(1, Attribute::StructRet))
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if (CS && !CS->paramHasAttr(1, Attribute::StructRet))
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return 0;
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if (CS.paramHasAttr(1, Attribute::InReg))
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if (CS && CS->paramHasAttr(1, Attribute::InReg))
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return 0;
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return 4;
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}
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@ -3025,7 +3027,7 @@ bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
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// Issue CALLSEQ_END
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unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
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const unsigned NumBytesCallee = computeBytesPoppedByCallee(*Subtarget, CS);
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unsigned NumBytesCallee = computeBytesPoppedByCallee(Subtarget, CC, &CS);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
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.addImm(NumBytes).addImm(NumBytesCallee);
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@ -3107,6 +3109,395 @@ bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
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return true;
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}
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bool X86FastISel::FastLowerCall(CallLoweringInfo &CLI) {
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auto &OutVals = CLI.OutVals;
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auto &OutFlags = CLI.OutFlags;
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auto &OutRegs = CLI.OutRegs;
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auto &Ins = CLI.Ins;
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auto &InRegs = CLI.InRegs;
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CallingConv::ID CC = CLI.CallConv;
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bool &IsTailCall = CLI.IsTailCall;
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bool IsVarArg = CLI.IsVarArg;
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const Value *Callee = CLI.Callee;
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const char *SymName = CLI.SymName;
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bool Is64Bit = Subtarget->is64Bit();
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bool IsWin64 = Subtarget->isCallingConvWin64(CC);
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// Handle only C, fastcc, and webkit_js calling conventions for now.
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switch (CC) {
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default: return false;
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case CallingConv::C:
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case CallingConv::Fast:
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case CallingConv::WebKit_JS:
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case CallingConv::X86_FastCall:
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case CallingConv::X86_64_Win64:
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case CallingConv::X86_64_SysV:
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break;
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}
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// Allow SelectionDAG isel to handle tail calls.
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if (IsTailCall)
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return false;
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// fastcc with -tailcallopt is intended to provide a guaranteed
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// tail call optimization. Fastisel doesn't know how to do that.
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if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt)
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return false;
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// Don't know how to handle Win64 varargs yet. Nothing special needed for
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// x86-32. Special handling for x86-64 is implemented.
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if (IsVarArg && IsWin64)
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return false;
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// Don't know about inalloca yet.
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if (CLI.CS && CLI.CS->hasInAllocaArgument())
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return false;
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// Fast-isel doesn't know about callee-pop yet.
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if (X86::isCalleePop(CC, Subtarget->is64Bit(), IsVarArg,
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TM.Options.GuaranteedTailCallOpt))
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return false;
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// If this is a constant i1/i8/i16 argument, promote to i32 to avoid an extra
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// instruction. This is safe because it is common to all FastISel supported
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// calling conventions on x86.
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for (int i = 0, e = OutVals.size(); i != e; ++i) {
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Value *&Val = OutVals[i];
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ISD::ArgFlagsTy Flags = OutFlags[i];
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if (auto *CI = dyn_cast<ConstantInt>(Val)) {
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if (CI->getBitWidth() < 32) {
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if (Flags.isSExt())
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Val = ConstantExpr::getSExt(CI, Type::getInt32Ty(CI->getContext()));
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else
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Val = ConstantExpr::getZExt(CI, Type::getInt32Ty(CI->getContext()));
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}
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}
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// Passing bools around ends up doing a trunc to i1 and passing it.
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// Codegen this as an argument + "and 1".
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if (auto *TI = dyn_cast<TruncInst>(Val)) {
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if (TI->getType()->isIntegerTy(1) && CLI.CS &&
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(TI->getParent() == CLI.CS->getInstruction()->getParent()) &&
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TI->hasOneUse()) {
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Val = cast<TruncInst>(Val)->getOperand(0);
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unsigned ResultReg = getRegForValue(Val);
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if (!ResultReg)
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return false;
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MVT ArgVT;
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if (!isTypeLegal(Val->getType(), ArgVT))
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return false;
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ResultReg =
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FastEmit_ri(ArgVT, ArgVT, ISD::AND, ResultReg, Val->hasOneUse(), 1);
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if (!ResultReg)
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return false;
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UpdateValueMap(Val, ResultReg);
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}
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}
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}
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, ArgLocs,
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CLI.RetTy->getContext());
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// Allocate shadow area for Win64
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if (IsWin64)
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CCInfo.AllocateStack(32, 8);
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SmallVector<MVT, 16> OutVTs;
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for (auto *Val : OutVals) {
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MVT VT;
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if (!isTypeLegal(Val->getType(), VT))
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return false;
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OutVTs.push_back(VT);
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}
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CCInfo.AnalyzeCallOperands(OutVTs, OutFlags, CC_X86);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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// Issue CALLSEQ_START
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unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
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.addImm(NumBytes);
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// Walk the register/memloc assignments, inserting copies/loads.
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const X86RegisterInfo *RegInfo =
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static_cast<const X86RegisterInfo *>(TM.getRegisterInfo());
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign const &VA = ArgLocs[i];
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const Value *ArgVal = OutVals[VA.getValNo()];
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MVT ArgVT = OutVTs[VA.getValNo()];
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if (ArgVT == MVT::x86mmx)
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return false;
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unsigned ArgReg = getRegForValue(ArgVal);
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if (!ArgReg)
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return false;
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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case CCValAssign::Full: break;
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case CCValAssign::SExt: {
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assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
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"Unexpected extend");
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bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg,
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ArgVT, ArgReg);
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assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
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ArgVT = VA.getLocVT();
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break;
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}
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case CCValAssign::ZExt: {
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assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
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"Unexpected extend");
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bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg,
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ArgVT, ArgReg);
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assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
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ArgVT = VA.getLocVT();
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break;
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}
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case CCValAssign::AExt: {
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assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
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"Unexpected extend");
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bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg,
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ArgVT, ArgReg);
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if (!Emitted)
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Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg,
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ArgVT, ArgReg);
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if (!Emitted)
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Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg,
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ArgVT, ArgReg);
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assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
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ArgVT = VA.getLocVT();
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break;
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}
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case CCValAssign::BCvt: {
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ArgReg = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, ArgReg,
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/*TODO: Kill=*/false);
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assert(ArgReg && "Failed to emit a bitcast!");
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ArgVT = VA.getLocVT();
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break;
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}
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case CCValAssign::VExt:
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// VExt has not been implemented, so this should be impossible to reach
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// for now. However, fallback to Selection DAG isel once implemented.
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return false;
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case CCValAssign::FPExt:
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llvm_unreachable("Unexpected loc info!");
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case CCValAssign::Indirect:
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// FIXME: Indirect doesn't need extending, but fast-isel doesn't fully
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// support this.
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return false;
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}
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if (VA.isRegLoc()) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
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OutRegs.push_back(VA.getLocReg());
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} else {
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assert(VA.isMemLoc());
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unsigned LocMemOffset = VA.getLocMemOffset();
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X86AddressMode AM;
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AM.Base.Reg = RegInfo->getStackRegister();
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AM.Disp = LocMemOffset;
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ISD::ArgFlagsTy Flags = OutFlags[VA.getValNo()];
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unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
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MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
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MachinePointerInfo::getStack(LocMemOffset), MachineMemOperand::MOStore,
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ArgVT.getStoreSize(), Alignment);
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if (Flags.isByVal()) {
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X86AddressMode SrcAM;
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SrcAM.Base.Reg = ArgReg;
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if (!TryEmitSmallMemcpy(AM, SrcAM, Flags.getByValSize()))
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return false;
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} else if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) {
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// If this is a really simple value, emit this with the Value* version
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// of X86FastEmitStore. If it isn't simple, we don't want to do this,
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// as it can cause us to reevaluate the argument.
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if (!X86FastEmitStore(ArgVT, ArgVal, AM, MMO))
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return false;
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} else {
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bool ValIsKill = hasTrivialKill(ArgVal);
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if (!X86FastEmitStore(ArgVT, ArgReg, ValIsKill, AM, MMO))
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return false;
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}
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}
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}
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// ELF / PIC requires GOT in the EBX register before function calls via PLT
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// GOT pointer.
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if (Subtarget->isPICStyleGOT()) {
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unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
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}
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if (Is64Bit && IsVarArg && !IsWin64) {
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// From AMD64 ABI document:
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// For calls that may call functions that use varargs or stdargs
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// (prototype-less calls or calls to functions containing ellipsis (...) in
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// the declaration) %al is used as hidden argument to specify the number
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// of SSE registers used. The contents of %al do not need to match exactly
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// the number of registers, but must be an ubound on the number of SSE
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// registers used and is in the range 0 - 8 inclusive.
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// Count the number of XMM registers allocated.
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static const MCPhysReg XMMArgRegs[] = {
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X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
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X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
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};
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unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
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assert((Subtarget->hasSSE1() || !NumXMMRegs)
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&& "SSE registers cannot be used when SSE is disabled");
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
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X86::AL).addImm(NumXMMRegs);
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}
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// Materialize callee address in a register. FIXME: GV address can be
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// handled with a CALLpcrel32 instead.
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X86AddressMode CalleeAM;
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if (!X86SelectCallAddress(Callee, CalleeAM))
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return false;
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unsigned CalleeOp = 0;
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const GlobalValue *GV = nullptr;
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if (CalleeAM.GV != nullptr) {
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GV = CalleeAM.GV;
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} else if (CalleeAM.Base.Reg != 0) {
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CalleeOp = CalleeAM.Base.Reg;
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} else
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return false;
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// Issue the call.
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MachineInstrBuilder MIB;
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if (CalleeOp) {
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// Register-indirect call.
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unsigned CallOpc = Is64Bit ? X86::CALL64r : CallOpc = X86::CALL32r;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc))
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.addReg(CalleeOp);
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} else {
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// Direct call.
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assert(GV && "Not a direct call");
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unsigned CallOpc = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32;
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// See if we need any target-specific flags on the GV operand.
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unsigned char OpFlags = 0;
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// On ELF targets, in both X86-64 and X86-32 mode, direct calls to
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// external symbols most go through the PLT in PIC mode. If the symbol
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// has hidden or protected visibility, or if it is static or local, then
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// we don't need to use the PLT - we can directly call it.
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if (Subtarget->isTargetELF() &&
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TM.getRelocationModel() == Reloc::PIC_ &&
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GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
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OpFlags = X86II::MO_PLT;
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} else if (Subtarget->isPICStyleStubAny() &&
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(GV->isDeclaration() || GV->isWeakForLinker()) &&
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(!Subtarget->getTargetTriple().isMacOSX() ||
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Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
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// PC-relative references to external symbols should go through $stub,
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// unless we're building with the leopard linker or later, which
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// automatically synthesizes these stubs.
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OpFlags = X86II::MO_DARWIN_STUB;
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}
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc));
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if (SymName)
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MIB.addExternalSymbol(SymName, OpFlags);
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else
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MIB.addGlobalAddress(GV, 0, OpFlags);
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}
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// Add a register mask operand representing the call-preserved registers.
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// Proper defs for return values will be added by setPhysRegsDeadExcept().
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MIB.addRegMask(TRI.getCallPreservedMask(CC));
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// Add an implicit use GOT pointer in EBX.
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if (Subtarget->isPICStyleGOT())
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MIB.addReg(X86::EBX, RegState::Implicit);
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if (Is64Bit && IsVarArg && !IsWin64)
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MIB.addReg(X86::AL, RegState::Implicit);
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// Add implicit physical register uses to the call.
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for (auto Reg : OutRegs)
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MIB.addReg(Reg, RegState::Implicit);
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// Issue CALLSEQ_END
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unsigned NumBytesForCalleeToPop =
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computeBytesPoppedByCallee(Subtarget, CC, CLI.CS);
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unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
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.addImm(NumBytes).addImm(NumBytesForCalleeToPop);
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// Now handle call return values.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs,
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CLI.RetTy->getContext());
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CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86);
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// Copy all of the result registers out of their specified physreg.
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unsigned ResultReg = FuncInfo.CreateRegs(CLI.RetTy);
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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EVT CopyVT = VA.getValVT();
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unsigned CopyReg = ResultReg + i;
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// If this is x86-64, and we disabled SSE, we can't return FP values
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if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
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((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
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report_fatal_error("SSE register return with SSE disabled");
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}
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// If this is a call to a function that returns an fp value on the floating
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// point stack, we must guarantee the value is popped from the stack, so
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// a COPY is not good enough - the copy instruction may be eliminated if the
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// return value is not used. We use the FpPOP_RETVAL instruction instead.
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if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
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// If we prefer to use the value in xmm registers, copy it out as f80 and
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// use a truncate to move it from fp stack reg to xmm reg.
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if (isScalarFPTypeInSSEReg(VA.getValVT())) {
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CopyVT = MVT::f80;
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CopyReg = createResultReg(&X86::RFP80RegClass);
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}
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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||||
TII.get(X86::FpPOP_RETVAL), CopyReg);
|
||||
|
||||
// Round the f80 to the right size, which also moves it to the appropriate
|
||||
// xmm register. This is accomplished by storing the f80 value in memory
|
||||
// and then loading it back.
|
||||
if (CopyVT != VA.getValVT()) {
|
||||
EVT ResVT = VA.getValVT();
|
||||
unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
|
||||
unsigned MemSize = ResVT.getSizeInBits()/8;
|
||||
int FI = MFI.CreateStackObject(MemSize, MemSize, false);
|
||||
addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
||||
TII.get(Opc)), FI)
|
||||
.addReg(CopyReg);
|
||||
Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
|
||||
addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
||||
TII.get(Opc), ResultReg + i), FI);
|
||||
}
|
||||
} else {
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
||||
TII.get(TargetOpcode::COPY), CopyReg).addReg(VA.getLocReg());
|
||||
InRegs.push_back(VA.getLocReg());
|
||||
}
|
||||
}
|
||||
|
||||
CLI.ResultReg = ResultReg;
|
||||
CLI.NumResultRegs = RVLocs.size();
|
||||
CLI.Call = MIB;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
X86FastISel::TargetSelectInstruction(const Instruction *I) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue