From 23937091f0edf16443dc46753d45a6fa545c6d23 Mon Sep 17 00:00:00 2001
From: Misha Brukman <brukman+llvm@gmail.com>
Date: Sat, 31 May 2003 06:25:19 +0000
Subject: [PATCH] The 'rd' register is consistently mentioned last in
 instruction definitions. Created new classes from which instructions inherit
 their ordering of fields.

llvm-svn: 6461
---
 llvm/lib/Target/Sparc/SparcV9_F3.td | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/Sparc/SparcV9_F3.td b/llvm/lib/Target/Sparc/SparcV9_F3.td
index 5083dad70ed3..ae8d06b33dd0 100644
--- a/llvm/lib/Target/Sparc/SparcV9_F3.td
+++ b/llvm/lib/Target/Sparc/SparcV9_F3.td
@@ -74,6 +74,18 @@ class F3_rs1simm13rd : F3_rs1simm13 {
   set Inst{29-25} = rd;
 }
 
+// F3_rs2 - Common class of instructions that don't use an rs1
+class F3_rs2 : F3 {
+  bits<5> rs2;
+  set Inst{4-0} = rs2;
+}
+
+// F3_rs2rd - Common class of instructions use rs2 and rd, but not rs1
+class F3_rs2rd : F3_rs2 {
+  bits<5> rd;
+  set Inst{29-25} = rd;
+}
+
 
 // Specific F3 classes...
 //
@@ -154,14 +166,14 @@ class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
   set Inst{4-0} = shcnt;
 }
 
-class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
+class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
   bits<6> shcnt;
-  bits<5> rs1;
+  bits<5> rd;
 
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
-  set Inst{18-14} = rs1;
+  set Inst{29-25} = rd;
   set Inst{13} = 1; // i field = 1
   set Inst{12} = 1; // x field = 1
   //set Inst{11-6} = dontcare;
@@ -169,7 +181,7 @@ class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
 }
 
 class F3_14<bits<2> opVal, bits<6> op3Val,
-            bits<9> opfval, string name> : F3_rdrs1rs2 {
+            bits<9> opfval, string name> : F3_rs2rd {
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;