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Change some patterns' format

This commit is contained in:
zhoujing 2023-01-17 09:34:59 +08:00
parent 2d601dc47f
commit 23821f9116
6 changed files with 46 additions and 61 deletions
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40
llvm/lib/Target/RISCV/VentusInstrInfoV.td
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@ -66,22 +66,23 @@ class DivergentNonPriStPat<PatFrag StoreOp, RVInst Inst>
// RVV instruction pattern class for float/interger ternary operations
// Dst is used to identify vx and vf
multiclass PatVXFTer<list<SDPatternOperator> Ops, DAGOperand Dst, ValueType Ty,
multiclass PatVXFTer<list<SDPatternOperator> Ops, ValueType Ty, DAGOperand Dst,
list<RVInst> Insts> {
def : Pat<(Ops[0] (Ops[1] (Ty VGPR:$rs1), (Ty VGPR:$rs2)),
(Ty VGPR:$rs3)), (Insts[0] VGPR:$rs2, VGPR:$rs1, VGPR:$rs3)>;
(Ty VGPR:$rs3)), (Insts[0] VGPR:$rs1, VGPR:$rs2, VGPR:$rs3)>;
def : Pat<(Ops[0] (Ops[1] (Ty Dst:$rs1), (Ty VGPR:$rs2)),
(Ty VGPR:$rs3)), (Insts[1] VGPR:$rs2, Dst:$rs1, VGPR:$rs3)>;
def : Pat<(Ops[0] (Ops[1] (Ty VGPR:$rs1), (Ty Dst:$rs2)),
(Ty VGPR:$rs3)), (Insts[1] VGPR:$rs1, Dst:$rs2, VGPR:$rs3)>;
// For fneg operation
// TODO: fneg operation is a little complicated
if !eq(!size(Insts), 4) then {
def : Pat<(Ops[0] (Ops[1] (fneg (Ty VGPR:$rs1)), (Ty VGPR:$rs2)),
(Ty VGPR:$rs3)), (Insts[2] VGPR:$rs2, VGPR:$rs1, VGPR:$rs3)>;
(Ty VGPR:$rs3)), (Insts[2] VGPR:$rs1, VGPR:$rs2, VGPR:$rs3)>;
def : Pat<(Ops[0] (Ops[1] (fneg (Ty Dst:$rs1)), (Ty VGPR:$rs2)),
(Ty VGPR:$rs3)), (Insts[3] VGPR:$rs2, Dst:$rs1, VGPR:$rs3)>;
def : Pat<(Ops[0] (Ops[1] (fneg (Ty VGPR:$rs1)), (Ty Dst:$rs2)),
(Ty VGPR:$rs3)), (Insts[3] VGPR:$rs1, Dst:$rs2, VGPR:$rs3)>;
}
}
@ -250,7 +251,7 @@ class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
// op vd, rs1, vs2 (reverse the order of rs1 and vs2)
class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVX<funct6, opv, (outs VGPR:$vd_wb),
(ins GPR:$rs1, VGPR:$vs2, VGPR:$vd),
(ins VGPR:$vd, GPR:$rs1, VGPR:$vs2),
opcodestr, "$vd, $rs1, $vs2">;
// op vd, vs2, imm
@ -980,7 +981,7 @@ let Constraints = "$vd_wb = $vs2" in {
defm VFMSAC_V : VMAC_FV_V_F<"vfmsac", 0b101110>;
defm VFNMSAC_V : VMAC_FV_V_F<"vfnmsac", 0b101111>;
}
let Constraints = "$vd = $vd_wb" in {
let Constraints = "$vd_wb = $vd" in {
defm VFMADD_V : VMAC_FV_V_F<"vfmadd", 0b101000>;
defm VFNMADD_V : VMAC_FV_V_F<"vfnmadd", 0b101001>;
defm VFMSUB_V : VMAC_FV_V_F<"vfmsub", 0b101010>;
@ -1149,7 +1150,6 @@ def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VGPR:$vd_wb),
// def : PatIntSetCC<[VGPR, GPR], SETUGT, VMSGTU_VX>;
// def : PatIntSetCC<[VGPR, uimm5], SETUGT, VMSGTU_VI>;
// TODO: need to add VX instruction support later
defm : PatVXIBin<DivergentBinFrag<smin>, [VMIN_VV, VMIN_VX]>;
defm : PatVXIBin<DivergentBinFrag<umin>, [VMINU_VV, VMINU_VX]>;
defm : PatVXIBin<DivergentBinFrag<smax>, [VMAX_VV, VMAX_VX]>;
@ -1176,8 +1176,8 @@ defm : PatVXIBin<DivergentBinFrag<setne>, [VMSNE_VV, VMSNE_VX, VMSNE_VI]>;
defm : PatVXIBin<DivergentBinFrag<seteq>, [VMSEQ_VV, VMSEQ_VX, VMSEQ_VI]>;
// Patterns for vrsub.vx and vrsub.vi
def : Pat<(sub GPR:$rs1, VGPR:$rs2), (VRSUB_VX VGPR:$rs2, GPR:$rs1)>;
def : Pat<(XLenVT (sub uimm5:$imm, (XLenVT VGPR:$rs1))),
(VRSUB_VI VGPR:$rs1, uimm5:$imm)>;
def : Pat<(XLenVT (sub uimm12:$imm, (XLenVT VGPR:$rs1))),
(VRSUB_VI VGPR:$rs1, uimm12:$imm)>;
// For now, some instructions are aliaed to other instructions
defm : SleOpePatVXIBin<[DivergentBinFrag<xor>, DivergentBinFrag<setlt>],
@ -1225,16 +1225,16 @@ def : Pat<(fabs (f32 VGPR:$rs1)), (VFSGNJX_VV $rs1, $rs1)>;
// Patterns for ternary operations
// TODO: vmacc/vfmacc, vnmsac/vfnmsac
defm : PatVXFTer<[DivergentBinFrag<fadd>, DivergentBinFrag<fmul>], GPRF32,
f32, [VFMADD_VV, VFMADD_VF]>;
defm : PatVXFTer<[DivergentBinFrag<fsub>, DivergentBinFrag<fmul>], GPRF32,
f32, [VFMSUB_VV, VFMSUB_VF, VFNMADD_VV, VFNMADD_VF]>;
defm : PatVXFTer<[DivergentBinFrag<fadd>, DivergentBinFrag<fmul>], f32,
GPRF32, [VFMADD_VV, VFMADD_VF]>;
defm : PatVXFTer<[DivergentBinFrag<fsub>, DivergentBinFrag<fmul>], f32,
GPRF32, [VFMSUB_VV, VFMSUB_VF, VFNMADD_VV, VFNMADD_VF]>;
defm : PatVXFTer<[ReverseDivergentBinFrag<fsub>, DivergentBinFrag<fmul>],
GPRF32, f32, [VFNMSUB_VV, VFNMSUB_VF]>;
defm : PatVXFTer<[DivergentBinFrag<add>, DivergentBinFrag<mul>], GPR,
XLenVT, [VMADD_VV, VMADD_VX]>;
f32, GPRF32, [VFNMSUB_VV, VFNMSUB_VF]>;
defm : PatVXFTer<[DivergentBinFrag<add>, DivergentBinFrag<mul>], XLenVT,
GPR, [VMADD_VV, VMADD_VX]>;
defm : PatVXFTer<[ReverseDivergentBinFrag<sub>, DivergentBinFrag<mul>],
GPR, XLenVT, [VNMSUB_VV, VNMSUB_VX]>;
XLenVT, GPR, [VNMSUB_VV, VNMSUB_VX]>;
// TODO: vfrec7.v? what is this
def : Pat<(any_fsqrt (f32 VGPR:$rs1)), (VFSQRT_V (f32 VGPR:$rs1))>;

4
llvm/test/CodeGen/RISCV/VentusGPGPU/addr-space2.ll
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@ -44,8 +44,8 @@ define spir_kernel void @foo(ptr addrspace(1) noundef align 4 %out) {
; VENTUS-NEXT: lw a2, 0(a0)
; VENTUS-NEXT: vmv.s.x v2, a1
; VENTUS-NEXT: vmv.s.x v3, a2
; VENTUS-NEXT: vmadd.vv v1, v2, v3
; VENTUS-NEXT: vsuxei32.v v1, (a0), v0
; VENTUS-NEXT: vmadd.vv v2, v1, v3
; VENTUS-NEXT: vsuxei32.v v2, (a0), v0
; VENTUS-NEXT: j .LBB0_3
; VENTUS-NEXT: .LBB0_2: # %if.else
; VENTUS-NEXT: slli a0, a0, 2

9
llvm/test/CodeGen/RISCV/VentusGPGPU/bitwise_logical.ll
View File

@ -2,15 +2,6 @@
; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=VENTUS %s
define float @vand_v(float %a, float %b) {
; VENTUS-LABEL: vand_v:
; VENTUS: # %bb.0:
; VENTUS-NEXT: vfadd.vv v0, v0, v1
; VENTUS-NEXT: ret
%1 = fadd float %a, %b
ret float %1
}
define i32 @vand_i(i32 %a) {
; VENTUS-LABEL: vand_i:
; VENTUS: # %bb.0:

9
llvm/test/CodeGen/RISCV/VentusGPGPU/branch.ll
View File

@ -6,17 +6,16 @@
define i32 @foo(i32 noundef %cond, i32 noundef %a, i32 noundef %b, i32 noundef %c) {
; VENTUS-LABEL: foo:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vadd.vx v4, v0, zero
; VENTUS-NEXT: vmv.s.x v5, zero
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vbeq v4, v5, .LBB0_2
; VENTUS-NEXT: vmv.s.x v4, zero
; VENTUS-NEXT: vbeq v0, v4, .LBB0_2
; VENTUS-NEXT: # %bb.1: # %entry
; VENTUS-NEXT: vjoin .LBB0_3
; VENTUS-NEXT: .LBB0_2: # %entry
; VENTUS-NEXT: vrsub.vi v3, v3, 0
; VENTUS-NEXT: vjoin .LBB0_3
; VENTUS-NEXT: .LBB0_3: # %entry
; VENTUS-NEXT: vmadd.vv v0, v2, v3
; VENTUS-NEXT: vmadd.vv v2, v1, v3
; VENTUS-NEXT: vadd.vx v0, v2, zero
; VENTUS-NEXT: ret
entry:
%tobool.not = icmp eq i32 %cond, 0

33
llvm/test/CodeGen/RISCV/VentusGPGPU/float.ll
View File

@ -297,8 +297,7 @@ entry:
define dso_local noundef float @fmadd(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmadd:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmadd.vv v1, v0, v2
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vfmadd.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, %b
@ -310,8 +309,7 @@ entry:
define dso_local noundef float @fmadd_llvm(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmadd_llvm:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmadd.vv v1, v0, v2
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vfmadd.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%0 = tail call float @llvm.fmuladd.f32(float %a, float %b, float %c)
@ -322,8 +320,7 @@ entry:
define dso_local noundef float @fmsub(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmsub:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmsub.vv v1, v0, v2
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vfmsub.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, %b
@ -379,8 +376,7 @@ entry:
define dso_local float @fmadd_v(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmadd_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmadd.vv v1, v0, v2
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vfmadd.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, %b
@ -394,7 +390,8 @@ define dso_local float @fmadd_f(float noundef %a, float noundef %b, float nounde
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(.LCPI24_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI24_0)(a0)
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vmv.s.x v1, a0
; VENTUS-NEXT: vfmadd.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
@ -406,8 +403,7 @@ entry:
define dso_local float @fnmadd_v(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fnmadd_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfnmadd.vv v1, v0, v2
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vfnmadd.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%0 = fneg float %a
@ -422,7 +418,8 @@ define dso_local float @fnmadd_f(float noundef %a, float noundef %b, float nound
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(.LCPI26_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI26_0)(a0)
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vmv.s.x v1, a0
; VENTUS-NEXT: vfmsub.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
@ -435,8 +432,7 @@ entry:
define dso_local float @fmsub_v(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmsub_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmsub.vv v1, v0, v2
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vfmsub.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, %b
@ -451,8 +447,7 @@ define dso_local float @fmsub_f(float noundef %a, float noundef %b) local_unname
; VENTUS-NEXT: lui a0, %hi(.LCPI28_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI28_0)(a0)
; VENTUS-NEXT: vmv.s.x v2, a0
; VENTUS-NEXT: vfmsub.vv v2, v0, v1
; VENTUS-NEXT: vadd.vx v0, v2, zero
; VENTUS-NEXT: vfmsub.vv v0, v2, v1
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, 0x3FF3333340000000
@ -464,8 +459,7 @@ entry:
define dso_local float @fnmsub_v(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fnmsub_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfnmsub.vv v1, v0, v2
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vfnmsub.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%0 = fmul float %a, %b
@ -479,7 +473,8 @@ define dso_local float @fnmsub_f(float noundef %a, float noundef %b, float nound
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(.LCPI30_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI30_0)(a0)
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vmv.s.x v1, a0
; VENTUS-NEXT: vfmadd.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:

12
llvm/test/CodeGen/RISCV/VentusGPGPU/int_arithmetic.ll
View File

@ -316,7 +316,8 @@ define i32 @vrsub_bigimm(i32 %a) nounwind {
define dso_local i32 @nmsub_v(i32 noundef %a, i32 noundef %b, i32 noundef %c) local_unnamed_addr {
; VENTUS-LABEL: nmsub_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vnmsub.vv v0, v1, v2
; VENTUS-NEXT: vnmsub.vv v1, v0, v2
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: ret
entry:
%mul = mul nsw i32 %b, %a
@ -331,8 +332,7 @@ define dso_local i32 @nmsub_x(i32 noundef %a, i32 noundef %b) local_unnamed_addr
; VENTUS-NEXT: lui a0, %hi(global_val)
; VENTUS-NEXT: lw a0, %lo(global_val)(a0)
; VENTUS-NEXT: vmv.s.x v2, a0
; VENTUS-NEXT: vmadd.vv v2, v0, v1
; VENTUS-NEXT: vadd.vx v0, v2, zero
; VENTUS-NEXT: vmadd.vv v0, v2, v1
; VENTUS-NEXT: ret
entry:
%val = load i32, ptr @global_val
@ -345,7 +345,8 @@ entry:
define dso_local i32 @madd_v(i32 noundef %a, i32 noundef %b, i32 noundef %c) local_unnamed_addr {
; VENTUS-LABEL: madd_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vmadd.vv v0, v1, v2
; VENTUS-NEXT: vmadd.vv v1, v0, v2
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: ret
entry:
%mul = mul nsw i32 %b, %a
@ -360,8 +361,7 @@ define dso_local i32 @madd_x(i32 noundef %a, i32 noundef %b) local_unnamed_addr
; VENTUS-NEXT: lui a0, %hi(global_val)
; VENTUS-NEXT: lw a0, %lo(global_val)(a0)
; VENTUS-NEXT: vmv.s.x v2, a0
; VENTUS-NEXT: vmadd.vv v2, v0, v1
; VENTUS-NEXT: vadd.vx v0, v2, zero
; VENTUS-NEXT: vmadd.vv v0, v2, v1
; VENTUS-NEXT: ret
entry:
%val = load i32, ptr @global_val