forked from OSchip/llvm-project
Bill Wendling
parent
de2aa65877
commit
2377206923
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@ -553,11 +553,125 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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//===----------------------------------------------------------------------===//
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// SSSE3
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// FP arithmetic ops
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// Horizontal arithmetic ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_ssse3_pmulhrsw_128 : GCCBuiltin<"__builtin_ia32_pmulhrsw128">,
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def int_x86_ssse3_phadd_w : GCCBuiltin<"__builtin_ia32_phaddw">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
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llvm_v4i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_phadd_w_128 : GCCBuiltin<"__builtin_ia32_phaddw128">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
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llvm_v8i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_phadd_d : GCCBuiltin<"__builtin_ia32_phaddd">,
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Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_ssse3_phadd_d_128 : GCCBuiltin<"__builtin_ia32_phaddd128">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
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llvm_v4i32_ty], [IntrNoMem]>;
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def int_x86_ssse3_phadd_sw : GCCBuiltin<"__builtin_ia32_phaddsw">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
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llvm_v4i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_phadd_sw_128 : GCCBuiltin<"__builtin_ia32_phaddsw128">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
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llvm_v4i32_ty], [IntrNoMem]>;
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def int_x86_ssse3_phsub_w : GCCBuiltin<"__builtin_ia32_phsubw">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
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llvm_v4i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_phsub_w_128 : GCCBuiltin<"__builtin_ia32_phsubw128">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
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llvm_v8i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_phsub_d : GCCBuiltin<"__builtin_ia32_phsubd">,
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Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_ssse3_phsub_d_128 : GCCBuiltin<"__builtin_ia32_phsubd128">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
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llvm_v4i32_ty], [IntrNoMem]>;
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def int_x86_ssse3_phsub_sw : GCCBuiltin<"__builtin_ia32_phsubsw">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
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llvm_v4i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_phsub_sw_128 : GCCBuiltin<"__builtin_ia32_phsubsw128">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
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llvm_v8i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_pmadd_ub_sw : GCCBuiltin<"__builtin_ia32_pmaddubsw">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
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llvm_v4i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_pmadd_ub_sw_128 : GCCBuiltin<"__builtin_ia32_pmaddubsw128">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
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llvm_v8i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_pmul_hr_sw : GCCBuiltin<"__builtin_ia32_pmulhrsw">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
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llvm_v4i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_pmul_hr_sw_128 : GCCBuiltin<"__builtin_ia32_pmulhrsw128">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
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llvm_v8i16_ty], [IntrNoMem]>;
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}
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// Shuffle ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_ssse3_pshuf_b : GCCBuiltin<"__builtin_ia32_pshufb">,
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Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty,
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llvm_v8i8_ty], [IntrNoMem]>;
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def int_x86_ssse3_pshuf_b_128 : GCCBuiltin<"__builtin_ia32_pshufb128">,
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty,
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llvm_v16i8_ty], [IntrNoMem]>;
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}
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// Sign ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_ssse3_psign_b : GCCBuiltin<"__builtin_ia32_psignb">,
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Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty,
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llvm_v8i8_ty], [IntrNoMem]>;
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def int_x86_ssse3_psign_b_128 : GCCBuiltin<"__builtin_ia32_psignb128">,
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty,
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llvm_v16i8_ty], [IntrNoMem]>;
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def int_x86_ssse3_psign_w : GCCBuiltin<"__builtin_ia32_psignw">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
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llvm_v4i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_psign_w_128 : GCCBuiltin<"__builtin_ia32_psignw128">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
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llvm_v8i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_psign_d : GCCBuiltin<"__builtin_ia32_psignd">,
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Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_ssse3_psign_d_128 : GCCBuiltin<"__builtin_ia32_psignd128">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
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llvm_v4i32_ty], [IntrNoMem]>;
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}
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// Absolute value ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_ssse3_pabs_b : GCCBuiltin<"__builtin_ia32_pabsb">,
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Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
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def int_x86_ssse3_pabs_b_128 : GCCBuiltin<"__builtin_ia32_pabsb128">,
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
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def int_x86_ssse3_pabs_w : GCCBuiltin<"__builtin_ia32_pabsw">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_pabs_w_128 : GCCBuiltin<"__builtin_ia32_pabsw128">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_pabs_d : GCCBuiltin<"__builtin_ia32_pabsd">,
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Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_ssse3_pabs_d_128 : GCCBuiltin<"__builtin_ia32_pabsd128">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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}
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// Align ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_ssse3_palign_r : GCCBuiltin<"__builtin_ia32_palignr">,
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Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
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llvm_v1i64_ty, llvm_i16_ty], [IntrNoMem]>;
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def int_x86_ssse3_palign_r_128 : GCCBuiltin<"__builtin_ia32_palignr128">,
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Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty,
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llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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@ -128,6 +128,11 @@ def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
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def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
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def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
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def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
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def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop node:$ptr))>;
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def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
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def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop node:$ptr))>;
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def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
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def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop node:$ptr))>;
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def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
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def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
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@ -2281,35 +2286,297 @@ let AddedComplexity = 20 in
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// SSE3 Instruction Templates:
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//
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// SS38I - SSSE3 instructions with T8 and OpSize prefixes.
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// SS3AI - SSSE3 instructions with TA and OpSize prefixes.
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// SS38I - SSSE3 instructions with T8 prefix.
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// SS3AI - SSSE3 instructions with TA prefix.
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class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, T8, OpSize, Requires<[HasSSSE3]>;
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: I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSSE3]>;
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class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TA, OpSize, Requires<[HasSSSE3]>;
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: I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSSE3]>;
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/// SS3I_binop_rm_int - Simple SSSE3 binary operatr whose type is v2i64.
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/// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
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let isTwoAddress = 1 in {
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multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
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bit Commutable = 0> {
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def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
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multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst, (IntId64 VR64:$src))]> {
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let isCommutable = Commutable;
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}
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def rm : SS38I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId VR128:$src1,
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(bitconvert (memopv2i64 addr:$src2))))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst,
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(IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (IntId128 VR128:$src))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId128
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(bitconvert (memopv16i8 addr:$src))))]>, OpSize;
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}
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}
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defm PMULHRSW128 : SS3I_binop_rm_int<0x0B, "pmulhrsw",
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int_x86_ssse3_pmulhrsw_128, 1>;
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/// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
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let isTwoAddress = 1 in {
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multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst, (IntId64 VR64:$src))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst,
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(IntId64
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(bitconvert (memopv4i16 addr:$src))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (IntId128 VR128:$src))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId128
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(bitconvert (memopv8i16 addr:$src))))]>, OpSize;
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}
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}
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/// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
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let isTwoAddress = 1 in {
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multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst, (IntId64 VR64:$src))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst,
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(IntId64
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(bitconvert (memopv2i32 addr:$src))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (IntId128 VR128:$src))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId128
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(bitconvert (memopv4i32 addr:$src))))]>, OpSize;
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}
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}
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defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
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int_x86_ssse3_pabs_b,
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int_x86_ssse3_pabs_b_128>;
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defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
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int_x86_ssse3_pabs_w,
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int_x86_ssse3_pabs_w_128>;
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defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
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int_x86_ssse3_pabs_d,
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int_x86_ssse3_pabs_d_128>;
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/// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
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let isTwoAddress = 1 in {
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multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
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Intrinsic IntId64, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
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let isCommutable = Commutable;
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}
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv8i8 addr:$src2))))]>;
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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}
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/// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
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let isTwoAddress = 1 in {
|
||||
multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
|
||||
Intrinsic IntId64, Intrinsic IntId128,
|
||||
bit Commutable = 0> {
|
||||
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
||||
(ins VR64:$src1, VR64:$src2),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
|
||||
let isCommutable = Commutable;
|
||||
}
|
||||
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
||||
(ins VR64:$src1, i64mem:$src2),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set VR64:$dst,
|
||||
(IntId64 VR64:$src1,
|
||||
(bitconvert (memopv4i16 addr:$src2))))]>;
|
||||
|
||||
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
||||
OpSize {
|
||||
let isCommutable = Commutable;
|
||||
}
|
||||
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins VR128:$src1, i128mem:$src2),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set VR128:$dst,
|
||||
(IntId128 VR128:$src1,
|
||||
(bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
|
||||
}
|
||||
}
|
||||
|
||||
/// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
|
||||
let isTwoAddress = 1 in {
|
||||
multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
|
||||
Intrinsic IntId64, Intrinsic IntId128,
|
||||
bit Commutable = 0> {
|
||||
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
||||
(ins VR64:$src1, VR64:$src2),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
|
||||
let isCommutable = Commutable;
|
||||
}
|
||||
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
||||
(ins VR64:$src1, i64mem:$src2),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set VR64:$dst,
|
||||
(IntId64 VR64:$src1,
|
||||
(bitconvert (memopv2i32 addr:$src2))))]>;
|
||||
|
||||
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
||||
OpSize {
|
||||
let isCommutable = Commutable;
|
||||
}
|
||||
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins VR128:$src1, i128mem:$src2),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set VR128:$dst,
|
||||
(IntId128 VR128:$src1,
|
||||
(bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
|
||||
}
|
||||
}
|
||||
|
||||
defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
|
||||
int_x86_ssse3_phadd_w,
|
||||
int_x86_ssse3_phadd_w_128, 1>;
|
||||
defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
|
||||
int_x86_ssse3_phadd_d,
|
||||
int_x86_ssse3_phadd_d_128, 1>;
|
||||
defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
|
||||
int_x86_ssse3_phadd_sw,
|
||||
int_x86_ssse3_phadd_sw_128, 1>;
|
||||
defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
|
||||
int_x86_ssse3_phsub_w,
|
||||
int_x86_ssse3_phsub_w_128>;
|
||||
defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
|
||||
int_x86_ssse3_phsub_d,
|
||||
int_x86_ssse3_phsub_d_128>;
|
||||
defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
|
||||
int_x86_ssse3_phsub_sw,
|
||||
int_x86_ssse3_phsub_sw_128>;
|
||||
defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
|
||||
int_x86_ssse3_pmadd_ub_sw,
|
||||
int_x86_ssse3_pmadd_ub_sw_128, 1>;
|
||||
defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
|
||||
int_x86_ssse3_pmul_hr_sw,
|
||||
int_x86_ssse3_pmul_hr_sw_128, 1>;
|
||||
defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
|
||||
int_x86_ssse3_pshuf_b,
|
||||
int_x86_ssse3_pshuf_b_128>;
|
||||
defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
|
||||
int_x86_ssse3_psign_b,
|
||||
int_x86_ssse3_psign_b_128>;
|
||||
defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
|
||||
int_x86_ssse3_psign_w,
|
||||
int_x86_ssse3_psign_w_128>;
|
||||
defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
|
||||
int_x86_ssse3_psign_d,
|
||||
int_x86_ssse3_psign_d_128>;
|
||||
|
||||
let isTwoAddress = 1 in {
|
||||
def PALIGN64rr : SS38I<0x0F, MRMSrcReg, (outs VR64:$dst),
|
||||
(ins VR64:$src1, VR64:$src2, i16imm:$src3),
|
||||
"palignr\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(int_x86_ssse3_palign_r
|
||||
VR64:$src1, VR64:$src2,
|
||||
imm:$src3))]>;
|
||||
def PALIGN64rm : SS38I<0x0F, MRMSrcReg, (outs VR64:$dst),
|
||||
(ins VR64:$src1, i64mem:$src2, i16imm:$src3),
|
||||
"palignr\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(int_x86_ssse3_palign_r
|
||||
VR64:$src1,
|
||||
(bitconvert (memopv2i32 addr:$src2)),
|
||||
imm:$src3))]>;
|
||||
|
||||
def PALIGN128rr : SS38I<0x0F, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, i32imm:$src3),
|
||||
"palignr\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_ssse3_palign_r_128
|
||||
VR128:$src1, VR128:$src2,
|
||||
imm:$src3))]>, OpSize;
|
||||
def PALIGN128rm : SS38I<0x0F, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, i128mem:$src2, i32imm:$src3),
|
||||
"palignr\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_ssse3_palign_r_128
|
||||
VR128:$src1,
|
||||
(bitconvert (memopv4i32 addr:$src2)),
|
||||
imm:$src3))]>, OpSize;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Non-Instruction Patterns
|
||||
|
|
|
|||
Loading…
Reference in New Issue