forked from OSchip/llvm-project
Add code to support stack spill/temp offsets that don't fit in the
immed. field. Moved insertCallerSavingCode() to PhyRegAlloc: it is now machine independent. Remove all uses of PhyRegAlloc. llvm-svn: 7391
This commit is contained in:
parent
9143f1962e
commit
2353584afc
llvm/lib/Target/Sparc
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@ -9,13 +9,11 @@
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#include "SparcRegClassInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionInfo.h"
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#include "llvm/CodeGen/PhyRegAlloc.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineInstrAnnot.h"
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#include "llvm/CodeGen/FunctionLiveVarInfo.h" // FIXME: Remove
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#include "../../CodeGen/RegAlloc/RegAllocCommon.h" // FIXME!
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#include "llvm/CodeGen/LiveRangeInfo.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iOther.h"
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#include "llvm/Function.h"
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@ -387,7 +385,8 @@ void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
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//---------------------------------------------------------------------------
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void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
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LiveRangeInfo &LRI,
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AddedInstrns *FirstAI) const {
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std::vector<MachineInstr*>& InstrnsBefore,
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std::vector<MachineInstr*>& InstrnsAfter) const {
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// check if this is a varArgs function. needed for choosing regs.
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bool isVarArgs = isVarArgsFunction(Meth->getType());
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@ -454,14 +453,14 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
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int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue(
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getSpilledRegSize(regType));
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cpReg2MemMI(FirstAI->InstrnsBefore,
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cpReg2MemMI(InstrnsBefore,
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UniArgReg, getFramePointer(), TmpOff, IntRegType);
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cpMem2RegMI(FirstAI->InstrnsBefore,
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cpMem2RegMI(InstrnsBefore,
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getFramePointer(), TmpOff, UniLRReg, regType);
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}
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else {
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cpReg2RegMI(FirstAI->InstrnsBefore, UniArgReg, UniLRReg, regType);
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cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
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}
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}
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else {
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@ -484,7 +483,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
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offsetFromFP += slotSize - argSize;
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}
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cpMem2RegMI(FirstAI->InstrnsBefore,
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cpMem2RegMI(InstrnsBefore,
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getFramePointer(), offsetFromFP, UniLRReg, regType);
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}
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@ -510,11 +509,11 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
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assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
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"This should only be an Int register for an FP argument");
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cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
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cpReg2MemMI(InstrnsBefore, UniArgReg,
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getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
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}
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else {
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cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
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cpReg2MemMI(InstrnsBefore, UniArgReg,
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getFramePointer(), LR->getSpillOffFromFP(), regType);
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}
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}
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@ -736,27 +735,51 @@ UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
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void
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UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcReg,
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unsigned DestPtrReg,
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unsigned PtrReg,
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int Offset, int RegType,
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int scratchReg) const {
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MachineInstr * MI = NULL;
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int OffReg = -1;
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// If the Offset will not fit in the signed-immediate field, find an
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// unused register to hold the offset value. This takes advantage of
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// the fact that all the opcodes used below have the same size immed. field.
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// Use the register allocator, PRA, to find an unused reg. at this MI.
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//
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if (RegType != IntCCRegType) // does not use offset below
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if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
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#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
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RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
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OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
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#else
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// Default to using register g2 for holding large offsets
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OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegClass::g4);
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#endif
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assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
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mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
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}
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switch (RegType) {
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case IntRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset));
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MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(DestPtrReg)
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.addSImm(Offset);
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if (target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset))
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MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
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else
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MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
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break;
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case FPSingleRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset));
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MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(DestPtrReg)
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.addSImm(Offset);
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if (target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset))
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MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
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else
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MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
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break;
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case FPDoubleRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset));
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MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(DestPtrReg)
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.addSImm(Offset);
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if (target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset))
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MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
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else
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MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
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break;
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case IntCCRegType:
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@ -768,15 +791,16 @@ UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
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.addMReg(scratchReg, MOTy::Def));
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mvec.push_back(MI);
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cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
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cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
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return;
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case FloatCCRegType: {
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assert(target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset));
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unsigned fsrRegNum = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
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unsigned fsrReg = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
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SparcSpecialRegClass::fsr);
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MI = BuildMI(V9::STXFSRi, 3)
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.addMReg(fsrRegNum).addMReg(DestPtrReg).addSImm(Offset);
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if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset))
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MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
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else
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MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg);
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break;
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}
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default:
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@ -794,35 +818,65 @@ UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
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void
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UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcPtrReg,
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unsigned PtrReg,
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int Offset,
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unsigned DestReg,
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int RegType,
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int scratchReg) const {
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MachineInstr * MI = NULL;
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int OffReg = -1;
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// If the Offset will not fit in the signed-immediate field, find an
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// unused register to hold the offset value. This takes advantage of
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// the fact that all the opcodes used below have the same size immed. field.
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// Use the register allocator, PRA, to find an unused reg. at this MI.
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//
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if (RegType != IntCCRegType) // does not use offset below
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if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
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#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
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RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
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OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
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#else
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// Default to using register g2 for holding large offsets
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OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegClass::g4);
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#endif
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assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
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mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
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}
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switch (RegType) {
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case IntRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset));
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MI = BuildMI(V9::LDXi, 3).addMReg(SrcPtrReg).addSImm(Offset)
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.addMReg(DestReg, MOTy::Def);
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if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
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MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
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MOTy::Def);
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else
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MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
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MOTy::Def);
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break;
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case FPSingleRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset));
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MI = BuildMI(V9::LDFi, 3).addMReg(SrcPtrReg).addSImm(Offset)
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.addMReg(DestReg, MOTy::Def);
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if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
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MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
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MOTy::Def);
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else
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MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
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MOTy::Def);
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break;
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case FPDoubleRegType:
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assert(target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset));
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MI = BuildMI(V9::LDDFi, 3).addMReg(SrcPtrReg).addSImm(Offset)
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.addMReg(DestReg, MOTy::Def);
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if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
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MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
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MOTy::Def);
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else
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MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
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MOTy::Def);
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break;
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case IntCCRegType:
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assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
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assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
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cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
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cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
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MI = (BuildMI(V9::WRCCRr, 3)
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.addMReg(scratchReg)
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.addMReg(SparcIntRegClass::g0)
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@ -831,10 +885,13 @@ UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
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break;
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case FloatCCRegType: {
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assert(target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset));
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unsigned fsrRegNum = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
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SparcSpecialRegClass::fsr);
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MI = BuildMI(V9::LDXFSRi, 3).addMReg(SrcPtrReg).addSImm(Offset)
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if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
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MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
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.addMReg(fsrRegNum, MOTy::UseAndDef);
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else
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MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
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.addMReg(fsrRegNum, MOTy::UseAndDef);
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break;
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}
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@ -877,202 +934,6 @@ UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
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//----------------------------------------------------------------------------
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// This method inserts caller saving/restoring instructons before/after
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// a call machine instruction. The caller saving/restoring instructions are
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// inserted like:
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//
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// ** caller saving instructions
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// other instructions inserted for the call by ColorCallArg
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// CALL instruction
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// other instructions inserted for the call ColorCallArg
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// ** caller restoring instructions
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//
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//----------------------------------------------------------------------------
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void
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UltraSparcRegInfo::insertCallerSavingCode
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(std::vector<MachineInstr*> &instrnsBefore,
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std::vector<MachineInstr*> &instrnsAfter,
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MachineInstr *CallMI,
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const BasicBlock *BB,
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PhyRegAlloc &PRA) const
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{
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assert(target.getInstrInfo().isCall(CallMI->getOpCode()));
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// has set to record which registers were saved/restored
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//
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hash_set<unsigned> PushedRegSet;
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CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
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// if the call is to a instrumentation function, do not insert save and
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// restore instructions the instrumentation function takes care of save
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// restore for volatile regs.
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//
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// FIXME: this should be made general, not specific to the reoptimizer!
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//
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const Function *Callee = argDesc->getCallInst()->getCalledFunction();
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bool isLLVMFirstTrigger = Callee && Callee->getName() == "llvm_first_trigger";
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// Now check if the call has a return value (using argDesc) and if so,
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// find the LR of the TmpInstruction representing the return value register.
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// (using the last or second-last *implicit operand* of the call MI).
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// Insert it to to the PushedRegSet since we must not save that register
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// and restore it after the call.
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// We do this because, we look at the LV set *after* the instruction
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// to determine, which LRs must be saved across calls. The return value
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// of the call is live in this set - but we must not save/restore it.
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//
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if (const Value *origRetVal = argDesc->getReturnValue()) {
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unsigned retValRefNum = (CallMI->getNumImplicitRefs() -
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(argDesc->getIndirectFuncPtr()? 1 : 2));
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const TmpInstruction* tmpRetVal =
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cast<TmpInstruction>(CallMI->getImplicitRef(retValRefNum));
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assert(tmpRetVal->getOperand(0) == origRetVal &&
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tmpRetVal->getType() == origRetVal->getType() &&
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"Wrong implicit ref?");
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LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( tmpRetVal );
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assert(RetValLR && "No LR for RetValue of call");
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if (! RetValLR->isMarkedForSpill())
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PushedRegSet.insert(getUnifiedRegNum(RetValLR->getRegClassID(),
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RetValLR->getColor()));
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}
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const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(CallMI, BB);
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ValueSet::const_iterator LIt = LVSetAft.begin();
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// for each live var in live variable set after machine inst
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for( ; LIt != LVSetAft.end(); ++LIt) {
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// get the live range corresponding to live var
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LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
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// LR can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if( LR ) {
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if(! LR->isMarkedForSpill()) {
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assert(LR->hasColor() && "LR is neither spilled nor colored?");
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unsigned RCID = LR->getRegClassID();
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unsigned Color = LR->getColor();
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if ( isRegVolatile(RCID, Color) ) {
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//if the function is special LLVM function,
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//And the register is not modified by call, don't save and restore
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if(isLLVMFirstTrigger && !modifiedByCall(RCID, Color))
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continue;
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// if the value is in both LV sets (i.e., live before and after
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// the call machine instruction)
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unsigned Reg = getUnifiedRegNum(RCID, Color);
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if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
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// if we haven't already pushed that register
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unsigned RegType = getRegTypeForLR(LR);
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// Now get two instructions - to push on stack and pop from stack
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// and add them to InstrnsBefore and InstrnsAfter of the
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// call instruction
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//
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int StackOff =
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PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType));
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//---- Insert code for pushing the reg on stack ----------
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std::vector<MachineInstr*> AdIBef, AdIAft;
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// We may need a scratch register to copy the saved value
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// to/from memory. This may itself have to insert code to
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// free up a scratch register. Any such code should go before
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// the save code. The scratch register, if any, is by default
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// temporary and not "used" by the instruction unless the
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// copy code itself decides to keep the value in the scratch reg.
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int scratchRegType = -1;
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int scratchReg = -1;
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if (regTypeNeedsScratchReg(RegType, scratchRegType))
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{ // Find a register not live in the LVSet before CallMI
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const ValueSet &LVSetBef =
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PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB);
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scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
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CallMI, AdIBef, AdIAft);
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assert(scratchReg != getInvalidRegNum());
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}
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if (AdIBef.size() > 0)
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instrnsBefore.insert(instrnsBefore.end(),
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AdIBef.begin(), AdIBef.end());
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cpReg2MemMI(instrnsBefore, Reg,getFramePointer(),StackOff,RegType,
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scratchReg);
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if (AdIAft.size() > 0)
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instrnsBefore.insert(instrnsBefore.end(),
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||||
AdIAft.begin(), AdIAft.end());
|
||||
|
||||
//---- Insert code for popping the reg from the stack ----------
|
||||
|
||||
AdIBef.clear();
|
||||
AdIAft.clear();
|
||||
|
||||
// We may need a scratch register to copy the saved value
|
||||
// from memory. This may itself have to insert code to
|
||||
// free up a scratch register. Any such code should go
|
||||
// after the save code. As above, scratch is not marked "used".
|
||||
//
|
||||
scratchRegType = -1;
|
||||
scratchReg = -1;
|
||||
if (regTypeNeedsScratchReg(RegType, scratchRegType))
|
||||
{ // Find a register not live in the LVSet after CallMI
|
||||
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
|
||||
CallMI, AdIBef, AdIAft);
|
||||
assert(scratchReg != getInvalidRegNum());
|
||||
}
|
||||
|
||||
if (AdIBef.size() > 0)
|
||||
instrnsAfter.insert(instrnsAfter.end(),
|
||||
AdIBef.begin(), AdIBef.end());
|
||||
|
||||
cpMem2RegMI(instrnsAfter, getFramePointer(), StackOff,Reg,RegType,
|
||||
scratchReg);
|
||||
|
||||
if (AdIAft.size() > 0)
|
||||
instrnsAfter.insert(instrnsAfter.end(),
|
||||
AdIAft.begin(), AdIAft.end());
|
||||
|
||||
PushedRegSet.insert(Reg);
|
||||
|
||||
if(DEBUG_RA) {
|
||||
std::cerr << "\nFor call inst:" << *CallMI;
|
||||
std::cerr << " -inserted caller saving instrs: Before:\n\t ";
|
||||
for_each(instrnsBefore.begin(), instrnsBefore.end(),
|
||||
std::mem_fun(&MachineInstr::dump));
|
||||
std::cerr << " -and After:\n\t ";
|
||||
for_each(instrnsAfter.begin(), instrnsAfter.end(),
|
||||
std::mem_fun(&MachineInstr::dump));
|
||||
}
|
||||
} // if not already pushed
|
||||
|
||||
} // if LR has a volatile color
|
||||
|
||||
} // if LR has color
|
||||
|
||||
} // if there is a LR for Var
|
||||
|
||||
} // for each value in the LV set after instruction
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Print the register assigned to a LR
|
||||
//---------------------------------------------------------------------------
|
||||
|
|
Loading…
Reference in New Issue