forked from OSchip/llvm-project
Add support for mergeable sections back into the XCore backend.
llvm-svn: 79368
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1f18b9a301
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@ -28,11 +28,24 @@ void XCoreTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){
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MCSectionXCore::SHF_DP_SECTION,
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SectionKind::getBSS(), false, getContext());
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// For now, disable lowering of mergable sections, just drop everything into
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// ReadOnly.
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MergeableConst4Section = 0;
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MergeableConst8Section = 0;
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MergeableConst16Section = 0;
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MergeableConst4Section =
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MCSectionXCore::Create(".cp.rodata.cst4", MCSectionELF::SHT_PROGBITS,
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MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_MERGE |
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MCSectionXCore::SHF_CP_SECTION,
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SectionKind::getMergeableConst4(), false,
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getContext());
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MergeableConst8Section =
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MCSectionXCore::Create(".cp.rodata.cst8", MCSectionELF::SHT_PROGBITS,
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MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_MERGE |
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MCSectionXCore::SHF_CP_SECTION,
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SectionKind::getMergeableConst8(), false,
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getContext());
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MergeableConst16Section =
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MCSectionXCore::Create(".cp.rodata.cst16", MCSectionELF::SHT_PROGBITS,
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MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_MERGE |
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MCSectionXCore::SHF_CP_SECTION,
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SectionKind::getMergeableConst16(), false,
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getContext());
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// TLS globals are lowered in the backend to arrays indexed by the current
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// thread id. After lowering they require no special handling by the linker
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@ -1,6 +1,6 @@
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; RUN: llvm-as < %s | llc -march=xcore -mcpu=xs1b-generic | FileCheck %s
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; CHECK: .section .cp.rodata,"ac",@progbits
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; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
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; CHECK: .LCPI1_0:
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; CHECK: .long 12345678
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; CHECK: f:
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@ -68,7 +68,7 @@ entry:
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; CHECK: G2:
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@G3 = constant i32 9401
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; CHECK: .section .cp.rodata,"ac",@progbits
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; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
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; CHECK: G3:
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@G4 = global i32* @G1
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