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[mips] [IAS] Outline NOP creation. NFC. 

Summary: Make the code more readable by outlining NOP creation.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8320

llvm-svn: 232371
This commit is contained in:
Toma Tabacu 2015-03-16 12:03:39 +00:00
parent 943483f451
commit 234482a54e
1 changed files with 26 additions and 22 deletions
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48
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -193,6 +193,9 @@ class MipsAsmParser : public MCTargetAsmParser {
bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
bool reportParseError(Twine ErrorMsg);
bool reportParseError(SMLoc Loc, Twine ErrorMsg);
@ -1367,22 +1370,11 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
}
}
// If this instruction has a delay slot and .set reorder is active,
// emit a NOP after it.
if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder()) {
// If this instruction has a delay slot and .set reorder is active,
// emit a NOP after it.
Instructions.push_back(Inst);
MCInst NopInst;
if (hasShortDelaySlot(Inst.getOpcode())) {
NopInst.setOpcode(Mips::MOVE16_MM);
NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
} else {
NopInst.setOpcode(Mips::SLL);
NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
NopInst.addOperand(MCOperand::CreateImm(0));
}
Instructions.push_back(NopInst);
createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Instructions);
return false;
}
@ -1984,14 +1976,10 @@ bool MipsAsmParser::expandUncondBranchMMPseudo(
}
Instructions.push_back(Inst);
if (AssemblerOptions.back()->isReorder()) {
// If .set reorder is active, emit a NOP after the branch instruction.
MCInst NopInst;
NopInst.setOpcode(Mips::MOVE16_MM);
NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
Instructions.push_back(NopInst);
}
// If .set reorder is active, emit a NOP after the branch instruction.
if (AssemblerOptions.back()->isReorder())
createNop(true, IDLoc, Instructions);
return false;
}
@ -2134,6 +2122,22 @@ MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
return false;
}
void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
MCInst NopInst;
if (hasShortDelaySlot) {
NopInst.setOpcode(Mips::MOVE16_MM);
NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
} else {
NopInst.setOpcode(Mips::SLL);
NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
NopInst.addOperand(MCOperand::CreateImm(0));
}
Instructions.push_back(NopInst);
}
unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
// As described by the Mips32r2 spec, the registers Rd and Rs for
// jalr.hb must be different.