forked from OSchip/llvm-project
[AArch64] Add pattern for SQDML*Lv1i32_indexed
There was no pattern to fold into these instructions. This patch adds the pattern obtained from the following ACLE intrinsics so that they generate sqdmlal/sqdmlsl instructions instead of separate sqdmull and sqadd/sqsub instructions: - vqdmlalh_s16, vqdmlslh_s16 - vqdmlalh_lane_s16, vqdmlalh_laneq_s16, vqdmlslh_lane_s16, vqdmlslh_laneq_s16 (when the lane index is 0) It also modifies the result of the existing pattern for the latter, when the lane index is not 0, to use the v1i32_indexed instructions instead of the v4i16_indexed ones. Fixes #49997. Differential Revision: https://reviews.llvm.org/D131700
This commit is contained in:
OverMighty
David Green
parent
d9993484ee
commit
232953f996
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@ -8847,20 +8847,6 @@ multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
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let Inst{20} = idx{0};
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}
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// FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
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// intermediate EXTRACT_SUBREG would be untyped.
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def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
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(i32 (vector_extract (v4i32
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(int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
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(v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
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VectorIndexH:$idx)))),
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(i64 0))))),
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(EXTRACT_SUBREG
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(!cast<Instruction>(NAME # v4i16_indexed)
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(SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
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V128_lo:$Rm, VectorIndexH:$idx),
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ssub)>;
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def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
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V128, V128,
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V128_lo, VectorIndexH,
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@ -8914,6 +8900,31 @@ multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
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let Inst{20} = idx{0};
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}
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def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
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(i32 (vector_extract
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(v4i32 (int_aarch64_neon_sqdmull
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(v4i16 V64:$Rn),
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(v4i16 V64:$Rm))),
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(i64 0))))),
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(!cast<Instruction>(NAME # v1i32_indexed)
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FPR32Op:$Rd,
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(EXTRACT_SUBREG V64:$Rn, hsub),
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(INSERT_SUBREG (IMPLICIT_DEF), V64:$Rm, dsub),
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(i64 0))>;
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def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
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(i32 (vector_extract
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(v4i32 (int_aarch64_neon_sqdmull
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(v4i16 V64:$Rn),
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(v4i16 (AArch64duplane16
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(v8i16 V128_lo:$Rm),
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VectorIndexH:$idx)))),
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(i64 0))))),
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(!cast<Instruction>(NAME # v1i32_indexed)
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FPR32Op:$Rd,
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(EXTRACT_SUBREG V64:$Rn, hsub),
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V128_lo:$Rm,
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VectorIndexH:$idx)>;
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def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
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FPR64Op, FPR32Op, V128, VectorIndexS,
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@ -1619,7 +1619,7 @@ define i32 @sqdmlal_lane_1s(i32 %A, i16 %B, <4 x i16> %C) nounwind {
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; CHECK-NEXT: fmov s1, w1
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; CHECK-NEXT: fmov s2, w0
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: sqdmlal.4s v2, v1, v0[1]
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; CHECK-NEXT: sqdmlal.h s2, h1, v0[1]
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; CHECK-NEXT: fmov w0, s2
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; CHECK-NEXT: ret
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%lhs = insertelement <4 x i16> undef, i16 %B, i32 0
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@ -1637,7 +1637,7 @@ define i32 @sqdmlsl_lane_1s(i32 %A, i16 %B, <4 x i16> %C) nounwind {
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; CHECK-NEXT: fmov s1, w1
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; CHECK-NEXT: fmov s2, w0
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: sqdmlsl.4s v2, v1, v0[1]
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; CHECK-NEXT: sqdmlsl.h s2, h1, v0[1]
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; CHECK-NEXT: fmov w0, s2
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; CHECK-NEXT: ret
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%lhs = insertelement <4 x i16> undef, i16 %B, i32 0
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@ -1649,6 +1649,38 @@ define i32 @sqdmlsl_lane_1s(i32 %A, i16 %B, <4 x i16> %C) nounwind {
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}
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declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32)
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define i32 @sqadd_lane1_sqdmull4s(i32 %A, <4 x i16> %B, <4 x i16> %C) nounwind {
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; CHECK-LABEL: sqadd_lane1_sqdmull4s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqdmull.4s v0, v0, v1
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; CHECK-NEXT: fmov s1, w0
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; CHECK-NEXT: mov.s w8, v0[1]
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: sqadd s0, s1, s0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%prod.vec = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %B, <4 x i16> %C)
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%prod = extractelement <4 x i32> %prod.vec, i32 1
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%res = call i32 @llvm.aarch64.neon.sqadd.i32(i32 %A, i32 %prod)
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ret i32 %res
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}
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define i32 @sqsub_lane1_sqdmull4s(i32 %A, <4 x i16> %B, <4 x i16> %C) nounwind {
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; CHECK-LABEL: sqsub_lane1_sqdmull4s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqdmull.4s v0, v0, v1
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; CHECK-NEXT: fmov s1, w0
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; CHECK-NEXT: mov.s w8, v0[1]
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: sqsub s0, s1, s0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%prod.vec = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %B, <4 x i16> %C)
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%prod = extractelement <4 x i32> %prod.vec, i32 1
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%res = call i32 @llvm.aarch64.neon.sqsub.i32(i32 %A, i32 %prod)
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ret i32 %res
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}
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define i64 @sqdmlal_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
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; CHECK-LABEL: sqdmlal_lane_1d:
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; CHECK: // %bb.0:
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@ -2894,6 +2926,23 @@ define <1 x double> @test_fdiv_v1f64(<1 x double> %L, <1 x double> %R) nounwind
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ret <1 x double> %prod
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}
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define i32 @sqdmlal_s(i16 %A, i16 %B, i32 %C) nounwind {
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; CHECK-LABEL: sqdmlal_s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w1
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; CHECK-NEXT: fmov s1, w0
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; CHECK-NEXT: fmov s2, w2
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; CHECK-NEXT: sqdmlal.h s2, h1, v0[0]
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; CHECK-NEXT: fmov w0, s2
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; CHECK-NEXT: ret
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%tmp1 = insertelement <4 x i16> undef, i16 %A, i64 0
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%tmp2 = insertelement <4 x i16> undef, i16 %B, i64 0
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%tmp3 = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
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%tmp4 = extractelement <4 x i32> %tmp3, i64 0
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%tmp5 = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %C, i32 %tmp4)
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ret i32 %tmp5
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}
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define i64 @sqdmlal_d(i32 %A, i32 %B, i64 %C) nounwind {
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; CHECK-LABEL: sqdmlal_d:
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; CHECK: // %bb.0:
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@ -2908,6 +2957,23 @@ define i64 @sqdmlal_d(i32 %A, i32 %B, i64 %C) nounwind {
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ret i64 %tmp5
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}
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define i32 @sqdmlsl_s(i16 %A, i16 %B, i32 %C) nounwind {
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; CHECK-LABEL: sqdmlsl_s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w1
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; CHECK-NEXT: fmov s1, w0
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; CHECK-NEXT: fmov s2, w2
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; CHECK-NEXT: sqdmlsl.h s2, h1, v0[0]
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; CHECK-NEXT: fmov w0, s2
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; CHECK-NEXT: ret
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%tmp1 = insertelement <4 x i16> undef, i16 %A, i64 0
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%tmp2 = insertelement <4 x i16> undef, i16 %B, i64 0
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%tmp3 = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
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%tmp4 = extractelement <4 x i32> %tmp3, i64 0
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%tmp5 = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %C, i32 %tmp4)
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ret i32 %tmp5
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}
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define i64 @sqdmlsl_d(i32 %A, i32 %B, i64 %C) nounwind {
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; CHECK-LABEL: sqdmlsl_d:
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; CHECK: // %bb.0:
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