forked from OSchip/llvm-project
The transform is:
(or (bool?A:B),(bool?C:D)) --> (bool?(or A,C):(or B,D)) By the time the OR is visited, both the SELECTs have been visited and not optimized and the OR itself hasn't been transformed so we do this transform in the hopes that the new ORs will be optimized. The transform is explicitly disabled for vector-selects until "codegen matures to handle them better". Patch by Muhammad Tauqir! llvm-svn: 175380
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@ -2071,6 +2071,20 @@ Instruction *InstCombiner::visitOr(BinaryOperator &I) {
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return BinaryOperator::CreateOr(Inner, C1);
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}
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// Change (or (bool?A:B),(bool?C:D)) --> (bool?(or A,C):(or B,D))
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// Since this OR statement hasn't been optimized further yet, we hope
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// that this transformation will allow the new ORs to be optimized.
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{
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Value *X = 0, *Y = 0;
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if (Op0->hasOneUse() && Op1->hasOneUse() &&
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match(Op0, m_Select(m_Value(X), m_Value(A), m_Value(B))) &&
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match(Op1, m_Select(m_Value(Y), m_Value(C), m_Value(D))) && X == Y) {
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Value *orTrue = Builder->CreateOr(A, C);
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Value *orFalse = Builder->CreateOr(B, D);
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return SelectInst::Create(X, orTrue, orFalse);
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}
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}
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return Changed ? &I : 0;
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}
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@ -10,10 +10,8 @@ define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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%j = or i32 %g, %i
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ret i32 %j
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; CHECK: %e = icmp slt i32 %a, %b
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; CHECK-NEXT: %g = select i1 %e, i32 %c, i32 0
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; CHECK-NEXT: %i = select i1 %e, i32 0, i32 %d
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; CHECK-NEXT: %j = or i32 %g, %i
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; CHECK-NEXT: ret i32 %j
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; CHECK-NEXT: [[result:%.*]] = select i1 %e, i32 %c, i32 %d
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; CHECK-NEXT: ret i32 [[result]]
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}
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define i32 @bar(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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%e = icmp slt i32 %a, %b
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@ -24,10 +22,8 @@ define i32 @bar(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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%j = or i32 %i, %g
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ret i32 %j
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; CHECK: %e = icmp slt i32 %a, %b
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; CHECK-NEXT: %g = select i1 %e, i32 %c, i32 0
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; CHECK-NEXT: %i = select i1 %e, i32 0, i32 %d
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; CHECK-NEXT: %j = or i32 %i, %g
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; CHECK-NEXT: ret i32 %j
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; CHECK-NEXT: [[result:%.*]] = select i1 %e, i32 %c, i32 %d
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; CHECK-NEXT: ret i32 [[result]]
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}
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define i32 @goo(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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@ -40,10 +36,8 @@ entry:
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%3 = or i32 %1, %2
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ret i32 %3
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; CHECK: %0 = icmp slt i32 %a, %b
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; CHECK-NEXT: %1 = select i1 %0, i32 %c, i32 0
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; CHECK-NEXT: %2 = select i1 %0, i32 0, i32 %d
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; CHECK-NEXT: %3 = or i32 %1, %2
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; CHECK-NEXT: ret i32 %3
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; CHECK-NEXT: [[result:%.*]] = select i1 %0, i32 %c, i32 %d
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; CHECK-NEXT: ret i32 [[result]]
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}
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define i32 @poo(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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entry:
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@ -55,10 +49,8 @@ entry:
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%3 = or i32 %1, %2
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ret i32 %3
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; CHECK: %0 = icmp slt i32 %a, %b
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; CHECK-NEXT: %1 = select i1 %0, i32 %c, i32 0
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; CHECK-NEXT: %2 = select i1 %0, i32 0, i32 %d
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; CHECK-NEXT: %3 = or i32 %1, %2
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; CHECK-NEXT: ret i32 %3
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; CHECK-NEXT: [[result:%.*]] = select i1 %0, i32 %c, i32 %d
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; CHECK-NEXT: ret i32 [[result]]
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}
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define i32 @par(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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@ -71,8 +63,6 @@ entry:
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%3 = or i32 %1, %2
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ret i32 %3
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; CHECK: %0 = icmp slt i32 %a, %b
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; CHECK-NEXT: %1 = select i1 %0, i32 %c, i32 0
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; CHECK-NEXT: %2 = select i1 %0, i32 0, i32 %d
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; CHECK-NEXT: %3 = or i32 %1, %2
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; CHECK-NEXT: ret i32 %3
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; CHECK-NEXT: [[result:%.*]] = select i1 %0, i32 %c, i32 %d
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; CHECK-NEXT: ret i32 [[result]]
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}
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@ -344,10 +344,9 @@ define <4 x i32> @test32(<4 x i1> %and.i1352, <4 x i32> %vecinit6.i176, <4 x i32
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%and.i = and <4 x i32> %vecinit6.i191, %neg.i ; <<4 x i32>> [#uses=1]
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%or.i = or <4 x i32> %and.i, %and.i129 ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %or.i
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; Don't turn this into a vector select until codegen matures to handle them
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; better.
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; codegen is mature enough to handle vector selects.
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; CHECK: @test32
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; CHECK: or <4 x i32> %and.i, %and.i129
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; CHECK: select <4 x i1> %and.i1352, <4 x i32> %vecinit6.i176, <4 x i32> %vecinit6.i191
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}
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define i1 @test33(i1 %X, i1 %Y) {
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