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[PowerPC] Expose some calling convention functions in PPCISelLowering.h. 

This is a preparatory patch for fast-isel support.  The instruction
selector will need to access some functions in PPCGenCallingConv.inc,
which in turn requires several helper functions to be defined.  These
are currently defined near the only use of PCCGenCallingConv.inc,
inside PPCISelLowering.cpp.  This patch moves the declaration of the
functions into the associated header file to provide the needed
visibility.

No functional change intended.

llvm-svn: 183844
This commit is contained in:
Bill Schmidt 2013-06-12 16:39:22 +00:00
parent fb3fc0bf34
commit 230b451389
2 changed files with 32 additions and 29 deletions
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43
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -37,21 +37,6 @@
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
using namespace llvm; using namespace llvm;
static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
MVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
MVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
@ -1769,18 +1754,18 @@ SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
#include "PPCGenCallingConv.inc" #include "PPCGenCallingConv.inc"
static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
CCValAssign::LocInfo &LocInfo, CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags, ISD::ArgFlagsTy &ArgFlags,
CCState &State) { CCState &State) {
return true; return true;
} }
static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
MVT &LocVT, MVT &LocVT,
CCValAssign::LocInfo &LocInfo, CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags, ISD::ArgFlagsTy &ArgFlags,
CCState &State) { CCState &State) {
static const uint16_t ArgRegs[] = { static const uint16_t ArgRegs[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R7, PPC::R8, PPC::R9, PPC::R10,
@ -1803,11 +1788,11 @@ static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
return false; return false;
} }
static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
MVT &LocVT, MVT &LocVT,
CCValAssign::LocInfo &LocInfo, CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags, ISD::ArgFlagsTy &ArgFlags,
CCState &State) { CCState &State) {
static const uint16_t ArgRegs[] = { static const uint16_t ArgRegs[] = {
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
PPC::F8 PPC::F8

18
llvm/lib/Target/PowerPC/PPCISelLowering.h
View File

@ -20,6 +20,7 @@
#include "PPCRegisterInfo.h" #include "PPCRegisterInfo.h"
#include "PPCSubtarget.h" #include "PPCSubtarget.h"
#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetLowering.h"
namespace llvm { namespace llvm {
@ -621,6 +622,23 @@ namespace llvm {
SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const; SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const;
SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const; SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const;
}; };
bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
MVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
MVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
} }
#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H