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[AArch64] add tests for vector bool math; NFC 

llvm-svn: 352519
This commit is contained in:
Sanjay Patel 2019-01-29 17:00:07 +00:00
parent 815cdbff29
commit 22dd34b0ec
1 changed files with 29 additions and 0 deletions
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29
llvm/test/CodeGen/AArch64/bool-ext-inc.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
define <4 x i32> @sextbool_add_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) {
; CHECK-LABEL: sextbool_add_vector:
; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ret
%c = icmp eq <4 x i32> %c1, %c2
%b = sext <4 x i1> %c to <4 x i32>
%s = add <4 x i32> %x, %b
ret <4 x i32> %s
}
define <4 x i32> @zextbool_sub_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) {
; CHECK-LABEL: zextbool_sub_vector:
; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: sub v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ret
%c = icmp eq <4 x i32> %c1, %c2
%b = zext <4 x i1> %c to <4 x i32>
%s = sub <4 x i32> %x, %b
ret <4 x i32> %s
}