forked from OSchip/llvm-project
[x86] Lower some trunc + shuffle patterns to vpmov[q|d][b|w]
This should help in lowering the following four intrinsics: _mm256_cvtepi32_epi8 _mm256_cvtepi64_epi16 _mm256_cvtepi64_epi8 _mm512_cvtepi64_epi8 Differential Revision: https://reviews.llvm.org/D46957 llvm-svn: 335238
This commit is contained in:
Mikhail Dvoretckii
parent
760d1d5741
commit
22c82af5c8
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@ -4822,10 +4822,24 @@ static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
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return true;
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}
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/// Return true if Val falls within the specified range (L, H].
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static bool isInRange(int Val, int Low, int Hi) {
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return (Val >= Low && Val < Hi);
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}
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/// Return true if the value of any element in Mask falls within the specified
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/// range (L, H].
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static bool isAnyInRange(ArrayRef<int> Mask, int Low, int Hi) {
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for (int M : Mask)
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if (isInRange(M, Low, Hi))
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return true;
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return false;
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}
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/// Return true if Val is undef or if its value falls within the
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/// specified range (L, H].
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static bool isUndefOrInRange(int Val, int Low, int Hi) {
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return (Val == SM_SentinelUndef) || (Val >= Low && Val < Hi);
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return (Val == SM_SentinelUndef) || isInRange(Val, Low, Hi);
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}
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/// Return true if every element in Mask is undef or if its value
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@ -4841,7 +4855,7 @@ static bool isUndefOrInRange(ArrayRef<int> Mask,
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/// Return true if Val is undef, zero or if its value falls within the
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/// specified range (L, H].
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static bool isUndefOrZeroOrInRange(int Val, int Low, int Hi) {
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return isUndefOrZero(Val) || (Val >= Low && Val < Hi);
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return isUndefOrZero(Val) || isInRange(Val, Low, Hi);
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}
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/// Return true if every element in Mask is undef, zero or if its value
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@ -4854,11 +4868,11 @@ static bool isUndefOrZeroOrInRange(ArrayRef<int> Mask, int Low, int Hi) {
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}
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/// Return true if every element in Mask, beginning
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/// from position Pos and ending in Pos+Size, falls within the specified
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/// sequential range (Low, Low+Size]. or is undef.
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static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
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unsigned Pos, unsigned Size, int Low) {
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for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
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/// from position Pos and ending in Pos + Size, falls within the specified
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/// sequence (Low, Low + Step, ..., Low + (Size - 1) * Step) or is undef.
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static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, unsigned Pos,
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unsigned Size, int Low, int Step = 1) {
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for (unsigned i = Pos, e = Pos + Size; i != e; ++i, Low += Step)
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if (!isUndefOrEqual(Mask[i], Low))
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return false;
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return true;
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@ -9390,6 +9404,99 @@ static SDValue lowerVectorShuffleWithUNPCK(const SDLoc &DL, MVT VT,
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return SDValue();
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}
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static bool matchVectorShuffleAsVPMOV(ArrayRef<int> Mask, bool SwappedOps,
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int Delta) {
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int Size = (int)Mask.size();
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int Split = Size / Delta;
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int TruncatedVectorStart = SwappedOps ? Size : 0;
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// Match for mask starting with e.g.: <8, 10, 12, 14,... or <0, 2, 4, 6,...
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if (!isSequentialOrUndefInRange(Mask, 0, Split, TruncatedVectorStart, Delta))
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return false;
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// The rest of the mask should not refer to the truncated vector's elements.
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if (isAnyInRange(Mask.slice(Split, Size - Split), TruncatedVectorStart,
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TruncatedVectorStart + Size))
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return false;
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return true;
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}
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// Try to lower trunc+vector_shuffle to a vpmovdb or a vpmovdw instruction.
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//
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// An example is the following:
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//
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// t0: ch = EntryToken
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// t2: v4i64,ch = CopyFromReg t0, Register:v4i64 %0
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// t25: v4i32 = truncate t2
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// t41: v8i16 = bitcast t25
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// t21: v8i16 = BUILD_VECTOR undef:i16, undef:i16, undef:i16, undef:i16,
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// Constant:i16<0>, Constant:i16<0>, Constant:i16<0>, Constant:i16<0>
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// t51: v8i16 = vector_shuffle<0,2,4,6,12,13,14,15> t41, t21
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// t18: v2i64 = bitcast t51
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//
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// Without avx512vl, this is lowered to:
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//
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// vpmovqd %zmm0, %ymm0
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// vpshufb {{.*#+}} xmm0 =
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// xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
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//
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// But when avx512vl is available, one can just use a single vpmovdw
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// instruction.
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static SDValue lowerVectorShuffleWithVPMOV(const SDLoc &DL, ArrayRef<int> Mask,
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MVT VT, SDValue V1, SDValue V2,
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SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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if (VT != MVT::v16i8 && VT != MVT::v8i16)
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return SDValue();
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if (Mask.size() != VT.getVectorNumElements())
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return SDValue();
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bool SwappedOps = false;
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if (!ISD::isBuildVectorAllZeros(V2.getNode())) {
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if (!ISD::isBuildVectorAllZeros(V1.getNode()))
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return SDValue();
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std::swap(V1, V2);
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SwappedOps = true;
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}
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// Look for:
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//
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// bitcast (truncate <8 x i32> %vec to <8 x i16>) to <16 x i8>
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// bitcast (truncate <4 x i64> %vec to <4 x i32>) to <8 x i16>
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//
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// and similar ones.
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if (V1.getOpcode() != ISD::BITCAST)
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return SDValue();
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if (V1.getOperand(0).getOpcode() != ISD::TRUNCATE)
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return SDValue();
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SDValue Src = V1.getOperand(0).getOperand(0);
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MVT SrcVT = Src.getSimpleValueType();
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// The vptrunc** instructions truncating 128 bit and 256 bit vectors
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// are only available with avx512vl.
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if (!SrcVT.is512BitVector() && !Subtarget.hasVLX())
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return SDValue();
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// Down Convert Word to Byte is only available with avx512bw. The case with
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// 256-bit output doesn't contain a shuffle and is therefore not handled here.
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if (SrcVT.getVectorElementType() == MVT::i16 && VT == MVT::v16i8 &&
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!Subtarget.hasBWI())
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return SDValue();
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// The first half/quarter of the mask should refer to every second/fourth
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// element of the vector truncated and bitcasted.
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if (!matchVectorShuffleAsVPMOV(Mask, SwappedOps, 2) &&
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!matchVectorShuffleAsVPMOV(Mask, SwappedOps, 4))
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return SDValue();
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return DAG.getNode(X86ISD::VTRUNC, DL, VT, Src);
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}
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// X86 has dedicated pack instructions that can handle specific truncation
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// operations: PACKSS and PACKUS.
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static bool matchVectorShuffleWithPACK(MVT VT, MVT &SrcVT, SDValue &V1,
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@ -14923,6 +15030,10 @@ static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget &Subtarget,
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if (canonicalizeShuffleMaskWithCommute(Mask))
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return DAG.getCommutedVectorShuffle(*SVOp);
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if (SDValue V =
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lowerVectorShuffleWithVPMOV(DL, Mask, VT, V1, V2, DAG, Subtarget))
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return V;
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// For each vector width, delegate to a specialized lowering routine.
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if (VT.is128BitVector())
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return lower128BitVectorShuffle(DL, Mask, VT, V1, V2, Zeroable, Subtarget,
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@ -511,8 +511,7 @@ define <2 x i64> @trunc_v8i32_to_v8i8_return_v2i64(<8 x i32> %vec) nounwind {
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;
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; AVX512VL-LABEL: trunc_v8i32_to_v8i8_return_v2i64:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512VL-NEXT: vzeroupper
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; AVX512VL-NEXT: retq
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;
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@ -526,15 +525,13 @@ define <2 x i64> @trunc_v8i32_to_v8i8_return_v2i64(<8 x i32> %vec) nounwind {
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;
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; AVX512BWVL-LABEL: trunc_v8i32_to_v8i8_return_v2i64:
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; AVX512BWVL: # %bb.0:
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; AVX512BWVL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512BWVL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512BWVL-NEXT: vzeroupper
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; AVX512BWVL-NEXT: retq
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;
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; AVX512VBMIVL-LABEL: trunc_v8i32_to_v8i8_return_v2i64:
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; AVX512VBMIVL: # %bb.0:
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; AVX512VBMIVL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512VBMIVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VBMIVL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512VBMIVL-NEXT: vzeroupper
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; AVX512VBMIVL-NEXT: retq
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%truncated.vec = trunc <8 x i32> %vec to <8 x i8>
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@ -573,8 +570,7 @@ define <16 x i8> @trunc_v8i32_to_v8i8_with_zext_return_v16i8(<8 x i32> %vec) nou
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;
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; AVX512VL-LABEL: trunc_v8i32_to_v8i8_with_zext_return_v16i8:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512VL-NEXT: vzeroupper
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; AVX512VL-NEXT: retq
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;
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@ -588,15 +584,13 @@ define <16 x i8> @trunc_v8i32_to_v8i8_with_zext_return_v16i8(<8 x i32> %vec) nou
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;
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; AVX512BWVL-LABEL: trunc_v8i32_to_v8i8_with_zext_return_v16i8:
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; AVX512BWVL: # %bb.0:
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; AVX512BWVL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512BWVL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512BWVL-NEXT: vzeroupper
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; AVX512BWVL-NEXT: retq
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;
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; AVX512VBMIVL-LABEL: trunc_v8i32_to_v8i8_with_zext_return_v16i8:
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; AVX512VBMIVL: # %bb.0:
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; AVX512VBMIVL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512VBMIVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VBMIVL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512VBMIVL-NEXT: vzeroupper
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; AVX512VBMIVL-NEXT: retq
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%truncated = trunc <8 x i32> %vec to <8 x i8>
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@ -636,8 +630,7 @@ define <16 x i8> @trunc_v8i32_to_v8i8_via_v8i16_return_v16i8(<8 x i32> %vec) nou
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;
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; AVX512VL-LABEL: trunc_v8i32_to_v8i8_via_v8i16_return_v16i8:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512VL-NEXT: vzeroupper
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; AVX512VL-NEXT: retq
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;
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@ -651,15 +644,13 @@ define <16 x i8> @trunc_v8i32_to_v8i8_via_v8i16_return_v16i8(<8 x i32> %vec) nou
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;
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; AVX512BWVL-LABEL: trunc_v8i32_to_v8i8_via_v8i16_return_v16i8:
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; AVX512BWVL: # %bb.0:
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; AVX512BWVL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512BWVL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512BWVL-NEXT: vzeroupper
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; AVX512BWVL-NEXT: retq
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;
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; AVX512VBMIVL-LABEL: trunc_v8i32_to_v8i8_via_v8i16_return_v16i8:
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; AVX512VBMIVL: # %bb.0:
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; AVX512VBMIVL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512VBMIVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VBMIVL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512VBMIVL-NEXT: vzeroupper
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; AVX512VBMIVL-NEXT: retq
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%truncated = trunc <8 x i32> %vec to <8 x i16>
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@ -698,8 +689,7 @@ define <16 x i8> @trunc_v8i32_to_v8i8_return_v16i8(<8 x i32> %vec) nounwind {
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;
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; AVX512VL-LABEL: trunc_v8i32_to_v8i8_return_v16i8:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512VL-NEXT: vzeroupper
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; AVX512VL-NEXT: retq
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;
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@ -713,15 +703,13 @@ define <16 x i8> @trunc_v8i32_to_v8i8_return_v16i8(<8 x i32> %vec) nounwind {
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;
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; AVX512BWVL-LABEL: trunc_v8i32_to_v8i8_return_v16i8:
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; AVX512BWVL: # %bb.0:
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; AVX512BWVL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512BWVL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512BWVL-NEXT: vzeroupper
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; AVX512BWVL-NEXT: retq
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;
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; AVX512VBMIVL-LABEL: trunc_v8i32_to_v8i8_return_v16i8:
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; AVX512VBMIVL: # %bb.0:
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; AVX512VBMIVL-NEXT: vpmovdw %ymm0, %xmm0
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; AVX512VBMIVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VBMIVL-NEXT: vpmovdb %ymm0, %xmm0
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; AVX512VBMIVL-NEXT: vzeroupper
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; AVX512VBMIVL-NEXT: retq
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%truncated = trunc <8 x i32> %vec to <8 x i8>
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@ -766,8 +754,7 @@ define <2 x i64> @trunc_v4i64_to_v4i16_return_v2i64(<4 x i64> %vec) nounwind {
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;
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; AVX512VL-LABEL: trunc_v4i64_to_v4i16_return_v2i64:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vpmovqd %ymm0, %xmm0
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; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VL-NEXT: vpmovqw %ymm0, %xmm0
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; AVX512VL-NEXT: vzeroupper
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; AVX512VL-NEXT: retq
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;
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@ -781,15 +768,13 @@ define <2 x i64> @trunc_v4i64_to_v4i16_return_v2i64(<4 x i64> %vec) nounwind {
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;
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; AVX512BWVL-LABEL: trunc_v4i64_to_v4i16_return_v2i64:
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; AVX512BWVL: # %bb.0:
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; AVX512BWVL-NEXT: vpmovqd %ymm0, %xmm0
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; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512BWVL-NEXT: vpmovqw %ymm0, %xmm0
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; AVX512BWVL-NEXT: vzeroupper
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; AVX512BWVL-NEXT: retq
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;
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; AVX512VBMIVL-LABEL: trunc_v4i64_to_v4i16_return_v2i64:
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; AVX512VBMIVL: # %bb.0:
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; AVX512VBMIVL-NEXT: vpmovqd %ymm0, %xmm0
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; AVX512VBMIVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX512VBMIVL-NEXT: vpmovqw %ymm0, %xmm0
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; AVX512VBMIVL-NEXT: vzeroupper
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; AVX512VBMIVL-NEXT: retq
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%truncated = trunc <4 x i64> %vec to <4 x i16>
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@ -833,8 +818,7 @@ define <8 x i16> @trunc_v4i64_to_v4i16_with_zext_return_v8i16(<4 x i64> %vec) no
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;
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; AVX512VL-LABEL: trunc_v4i64_to_v4i16_with_zext_return_v8i16:
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; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX512VL-NEXT: vpmovqw %ymm0, %xmm0
|
||||
; AVX512VL-NEXT: vzeroupper
|
||||
; AVX512VL-NEXT: retq
|
||||
;
|
||||
|
|
@ -848,15 +832,13 @@ define <8 x i16> @trunc_v4i64_to_v4i16_with_zext_return_v8i16(<4 x i64> %vec) no
|
|||
;
|
||||
; AVX512BWVL-LABEL: trunc_v4i64_to_v4i16_with_zext_return_v8i16:
|
||||
; AVX512BWVL: # %bb.0:
|
||||
; AVX512BWVL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX512BWVL-NEXT: vpmovqw %ymm0, %xmm0
|
||||
; AVX512BWVL-NEXT: vzeroupper
|
||||
; AVX512BWVL-NEXT: retq
|
||||
;
|
||||
; AVX512VBMIVL-LABEL: trunc_v4i64_to_v4i16_with_zext_return_v8i16:
|
||||
; AVX512VBMIVL: # %bb.0:
|
||||
; AVX512VBMIVL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512VBMIVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX512VBMIVL-NEXT: vpmovqw %ymm0, %xmm0
|
||||
; AVX512VBMIVL-NEXT: vzeroupper
|
||||
; AVX512VBMIVL-NEXT: retq
|
||||
%truncated = trunc <4 x i64> %vec to <4 x i16>
|
||||
|
|
@ -901,8 +883,7 @@ define <8 x i16> @trunc_v4i64_to_v4i16_via_v4i32_return_v8i16(<4 x i64> %vec) no
|
|||
;
|
||||
; AVX512VL-LABEL: trunc_v4i64_to_v4i16_via_v4i32_return_v8i16:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX512VL-NEXT: vpmovqw %ymm0, %xmm0
|
||||
; AVX512VL-NEXT: vzeroupper
|
||||
; AVX512VL-NEXT: retq
|
||||
;
|
||||
|
|
@ -916,15 +897,13 @@ define <8 x i16> @trunc_v4i64_to_v4i16_via_v4i32_return_v8i16(<4 x i64> %vec) no
|
|||
;
|
||||
; AVX512BWVL-LABEL: trunc_v4i64_to_v4i16_via_v4i32_return_v8i16:
|
||||
; AVX512BWVL: # %bb.0:
|
||||
; AVX512BWVL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX512BWVL-NEXT: vpmovqw %ymm0, %xmm0
|
||||
; AVX512BWVL-NEXT: vzeroupper
|
||||
; AVX512BWVL-NEXT: retq
|
||||
;
|
||||
; AVX512VBMIVL-LABEL: trunc_v4i64_to_v4i16_via_v4i32_return_v8i16:
|
||||
; AVX512VBMIVL: # %bb.0:
|
||||
; AVX512VBMIVL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512VBMIVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX512VBMIVL-NEXT: vpmovqw %ymm0, %xmm0
|
||||
; AVX512VBMIVL-NEXT: vzeroupper
|
||||
; AVX512VBMIVL-NEXT: retq
|
||||
%truncated = trunc <4 x i64> %vec to <4 x i32>
|
||||
|
|
@ -968,8 +947,7 @@ define <8 x i16> @trunc_v4i64_to_v4i16_return_v8i16(<4 x i64> %vec) nounwind {
|
|||
;
|
||||
; AVX512VL-LABEL: trunc_v4i64_to_v4i16_return_v8i16:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX512VL-NEXT: vpmovqw %ymm0, %xmm0
|
||||
; AVX512VL-NEXT: vzeroupper
|
||||
; AVX512VL-NEXT: retq
|
||||
;
|
||||
|
|
@ -983,15 +961,13 @@ define <8 x i16> @trunc_v4i64_to_v4i16_return_v8i16(<4 x i64> %vec) nounwind {
|
|||
;
|
||||
; AVX512BWVL-LABEL: trunc_v4i64_to_v4i16_return_v8i16:
|
||||
; AVX512BWVL: # %bb.0:
|
||||
; AVX512BWVL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX512BWVL-NEXT: vpmovqw %ymm0, %xmm0
|
||||
; AVX512BWVL-NEXT: vzeroupper
|
||||
; AVX512BWVL-NEXT: retq
|
||||
;
|
||||
; AVX512VBMIVL-LABEL: trunc_v4i64_to_v4i16_return_v8i16:
|
||||
; AVX512VBMIVL: # %bb.0:
|
||||
; AVX512VBMIVL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512VBMIVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX512VBMIVL-NEXT: vpmovqw %ymm0, %xmm0
|
||||
; AVX512VBMIVL-NEXT: vzeroupper
|
||||
; AVX512VBMIVL-NEXT: retq
|
||||
%truncated = trunc <4 x i64> %vec to <4 x i16>
|
||||
|
|
@ -1034,8 +1010,7 @@ define <16 x i8> @trunc_v4i64_to_v4i8_return_v16i8(<4 x i64> %vec) nounwind {
|
|||
;
|
||||
; AVX512VL-LABEL: trunc_v4i64_to_v4i8_return_v16i8:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[u],zero
|
||||
; AVX512VL-NEXT: vpmovqb %ymm0, %xmm0
|
||||
; AVX512VL-NEXT: vzeroupper
|
||||
; AVX512VL-NEXT: retq
|
||||
;
|
||||
|
|
@ -1049,15 +1024,13 @@ define <16 x i8> @trunc_v4i64_to_v4i8_return_v16i8(<4 x i64> %vec) nounwind {
|
|||
;
|
||||
; AVX512BWVL-LABEL: trunc_v4i64_to_v4i8_return_v16i8:
|
||||
; AVX512BWVL: # %bb.0:
|
||||
; AVX512BWVL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[u],zero
|
||||
; AVX512BWVL-NEXT: vpmovqb %ymm0, %xmm0
|
||||
; AVX512BWVL-NEXT: vzeroupper
|
||||
; AVX512BWVL-NEXT: retq
|
||||
;
|
||||
; AVX512VBMIVL-LABEL: trunc_v4i64_to_v4i8_return_v16i8:
|
||||
; AVX512VBMIVL: # %bb.0:
|
||||
; AVX512VBMIVL-NEXT: vpmovqd %ymm0, %xmm0
|
||||
; AVX512VBMIVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[u],zero
|
||||
; AVX512VBMIVL-NEXT: vpmovqb %ymm0, %xmm0
|
||||
; AVX512VBMIVL-NEXT: vzeroupper
|
||||
; AVX512VBMIVL-NEXT: retq
|
||||
%truncated = trunc <4 x i64> %vec to <4 x i8>
|
||||
|
|
|
|||
|
|
@ -945,8 +945,7 @@ define <4 x double> @PR34175(<32 x i16>* %p) {
|
|||
define <16 x i8> @trunc_v8i64_to_v8i8_return_v16i8(<8 x i64> %vec) nounwind {
|
||||
; AVX512-LABEL: trunc_v8i64_to_v8i8_return_v16i8:
|
||||
; AVX512: # %bb.0:
|
||||
; AVX512-NEXT: vpmovqw %zmm0, %xmm0
|
||||
; AVX512-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX512-NEXT: vpmovqb %zmm0, %xmm0
|
||||
; AVX512-NEXT: vzeroupper
|
||||
; AVX512-NEXT: retq
|
||||
%truncated = trunc <8 x i64> %vec to <8 x i8>
|
||||
|
|
|
|||
Loading…
Reference in New Issue