forked from OSchip/llvm-project
[PhaseOrdering] add tests for reductions; NFC (PR43953)
This commit is contained in:
Sanjay Patel
parent
7928f2c177
commit
22c4c6dd38
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@ -63,3 +63,246 @@ define i32 @ext_ext_partial_add_reduction_and_extra_add_v4i32(<4 x i32> %x, <4 x
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%x2y210 = add i32 %x2, %y210
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%x2y210 = add i32 %x2, %y210
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ret i32 %x2y210
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ret i32 %x2y210
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}
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}
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; PR43953 - https://bugs.llvm.org/show_bug.cgi?id=43953
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; We want to end up with a single reduction on the next 4 tests.
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define i32 @TestVectorsEqual(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
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; CHECK-LABEL: @TestVectorsEqual(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[VEC0:%.*]] to <4 x i32>*
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[VEC1:%.*]] to <4 x i32>*
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; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4
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; CHECK-NEXT: [[TMP4:%.*]] = sub nsw <4 x i32> [[TMP1]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], zeroinitializer
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; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <4 x i32> zeroinitializer, [[TMP4]]
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; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP4]]
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP7]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x i32> [[BIN_RDX]], <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX4:%.*]] = add <4 x i32> [[BIN_RDX]], [[RDX_SHUF3]]
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; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[BIN_RDX4]], i32 0
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; CHECK-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP8]], [[TOLERANCE:%.*]]
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; CHECK-NEXT: [[COND6:%.*]] = zext i1 [[CMP5]] to i32
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; CHECK-NEXT: ret i32 [[COND6]]
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;
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entry:
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br label %for.cond
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for.cond:
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%sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
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%Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp = icmp slt i32 %Component.0, 4
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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br label %for.end
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for.body:
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%idxprom = sext i32 %Component.0 to i64
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%arrayidx = getelementptr inbounds i32, i32* %Vec0, i64 %idxprom
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%0 = load i32, i32* %arrayidx, align 4
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%idxprom1 = sext i32 %Component.0 to i64
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%arrayidx2 = getelementptr inbounds i32, i32* %Vec1, i64 %idxprom1
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%1 = load i32, i32* %arrayidx2, align 4
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%sub = sub nsw i32 %0, %1
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%cmp3 = icmp sge i32 %sub, 0
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br i1 %cmp3, label %cond.true, label %cond.false
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cond.true:
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br label %cond.end
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cond.false:
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%sub4 = sub nsw i32 0, %sub
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %sub, %cond.true ], [ %sub4, %cond.false ]
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%add = add nsw i32 %sum.0, %cond
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br label %for.inc
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for.inc:
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%inc = add nsw i32 %Component.0, 1
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br label %for.cond
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for.end:
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%cmp5 = icmp sle i32 %sum.0, %Tolerance
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%2 = zext i1 %cmp5 to i64
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%cond6 = select i1 %cmp5, i32 1, i32 0
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ret i32 %cond6
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}
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define i32 @TestVectorsEqual_alt(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
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; CHECK-LABEL: @TestVectorsEqual_alt(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[VEC0:%.*]] to <4 x i32>*
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[VEC1:%.*]] to <4 x i32>*
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; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4
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; CHECK-NEXT: [[RDX_SHUF5:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX6:%.*]] = add <4 x i32> [[TMP1]], [[RDX_SHUF5]]
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; CHECK-NEXT: [[RDX_SHUF7:%.*]] = shufflevector <4 x i32> [[BIN_RDX6]], <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[BIN_RDX6]], [[RDX_SHUF7]]
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP3]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x i32> [[BIN_RDX]], <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX4:%.*]] = add <4 x i32> [[BIN_RDX]], [[RDX_SHUF3]]
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; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[BIN_RDX8]], [[BIN_RDX4]]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0
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; CHECK-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP5]], [[TOLERANCE:%.*]]
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; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP3]] to i32
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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br label %for.cond
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for.cond:
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%sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
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%Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp = icmp slt i32 %Component.0, 4
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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br label %for.end
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for.body:
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%idxprom = sext i32 %Component.0 to i64
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%arrayidx = getelementptr inbounds i32, i32* %Vec0, i64 %idxprom
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%0 = load i32, i32* %arrayidx, align 4
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%idxprom1 = sext i32 %Component.0 to i64
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%arrayidx2 = getelementptr inbounds i32, i32* %Vec1, i64 %idxprom1
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%1 = load i32, i32* %arrayidx2, align 4
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%sub = sub i32 %0, %1
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%add = add i32 %sum.0, %sub
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br label %for.inc
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for.inc:
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%inc = add nsw i32 %Component.0, 1
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br label %for.cond
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for.end:
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%cmp3 = icmp ule i32 %sum.0, %Tolerance
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%2 = zext i1 %cmp3 to i64
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%cond = select i1 %cmp3, i32 1, i32 0
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ret i32 %cond
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}
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define i32 @TestVectorsEqualFP(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
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; CHECK-LABEL: @TestVectorsEqualFP(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[VEC0:%.*]] to <4 x float>*
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[VEC1:%.*]] to <4 x float>*
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; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, <4 x float>* [[TMP2]], align 4
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; CHECK-NEXT: [[TMP4:%.*]] = fsub fast <4 x float> [[TMP1]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[TMP5]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX4:%.*]] = fadd fast <4 x float> [[BIN_RDX]], [[RDX_SHUF3]]
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[BIN_RDX4]], i32 0
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; CHECK-NEXT: [[CMP4:%.*]] = fcmp fast ole float [[TMP6]], [[TOLERANCE:%.*]]
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; CHECK-NEXT: [[COND5:%.*]] = zext i1 [[CMP4]] to i32
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; CHECK-NEXT: ret i32 [[COND5]]
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;
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entry:
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br label %for.cond
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for.cond:
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%sum.0 = phi float [ 0.000000e+00, %entry ], [ %add, %for.inc ]
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%Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp = icmp slt i32 %Component.0, 4
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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br label %for.end
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for.body:
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%idxprom = sext i32 %Component.0 to i64
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%arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom
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%0 = load float, float* %arrayidx, align 4
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%idxprom1 = sext i32 %Component.0 to i64
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%arrayidx2 = getelementptr inbounds float, float* %Vec1, i64 %idxprom1
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%1 = load float, float* %arrayidx2, align 4
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%sub = fsub fast float %0, %1
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%cmp3 = fcmp fast oge float %sub, 0.000000e+00
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br i1 %cmp3, label %cond.true, label %cond.false
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cond.true:
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br label %cond.end
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cond.false:
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%fneg = fneg fast float %sub
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br label %cond.end
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cond.end:
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%cond = phi fast float [ %sub, %cond.true ], [ %fneg, %cond.false ]
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%add = fadd fast float %sum.0, %cond
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br label %for.inc
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for.inc:
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%inc = add nsw i32 %Component.0, 1
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br label %for.cond
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for.end:
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%cmp4 = fcmp fast ole float %sum.0, %Tolerance
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%2 = zext i1 %cmp4 to i64
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%cond5 = select i1 %cmp4, i32 1, i32 0
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ret i32 %cond5
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}
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define i32 @TestVectorsEqualFP_alt(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
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; CHECK-LABEL: @TestVectorsEqualFP_alt(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[VEC0:%.*]] to <4 x float>*
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[VEC1:%.*]] to <4 x float>*
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; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, <4 x float>* [[TMP2]], align 4
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; CHECK-NEXT: [[RDX_SHUF5:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX6:%.*]] = fadd fast <4 x float> [[TMP1]], [[RDX_SHUF5]]
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; CHECK-NEXT: [[RDX_SHUF7:%.*]] = shufflevector <4 x float> [[BIN_RDX6]], <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX8:%.*]] = fadd fast <4 x float> [[BIN_RDX6]], [[RDX_SHUF7]]
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[TMP3]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX4:%.*]] = fadd fast <4 x float> [[BIN_RDX]], [[RDX_SHUF3]]
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; CHECK-NEXT: [[TMP4:%.*]] = fsub fast <4 x float> [[BIN_RDX8]], [[BIN_RDX4]]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP4]], i32 0
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; CHECK-NEXT: [[CMP3:%.*]] = fcmp fast ole float [[TMP5]], [[TOLERANCE:%.*]]
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; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP3]] to i32
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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br label %for.cond
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for.cond:
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%sum.0 = phi float [ 0.000000e+00, %entry ], [ %add, %for.inc ]
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%Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp = icmp slt i32 %Component.0, 4
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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br label %for.end
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for.body:
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%idxprom = sext i32 %Component.0 to i64
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%arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom
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%0 = load float, float* %arrayidx, align 4
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%idxprom1 = sext i32 %Component.0 to i64
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%arrayidx2 = getelementptr inbounds float, float* %Vec1, i64 %idxprom1
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%1 = load float, float* %arrayidx2, align 4
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%sub = fsub fast float %0, %1
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%add = fadd fast float %sum.0, %sub
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br label %for.inc
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for.inc:
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%inc = add nsw i32 %Component.0, 1
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br label %for.cond
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for.end:
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%cmp3 = fcmp fast ole float %sum.0, %Tolerance
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%2 = zext i1 %cmp3 to i64
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%cond = select i1 %cmp3, i32 1, i32 0
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ret i32 %cond
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}
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