forked from OSchip/llvm-project
Update instructions for vector load/store
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@ -258,6 +258,8 @@ def GPRMemZeroOffset : MemOperand<GPR> {
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def GPRMem : MemOperand<GPR>;
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def VGPRMem : MemOperand<VGPR>;
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def TPMem : MemOperand<TP>;
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def GPRCMem : MemOperand<GPRC>;
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@ -707,6 +707,15 @@ class Branch_i<bits<3> funct3, string opcodestr>
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let vs2 = 0;
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}
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class VENTUS_VLWI12<bits<3> funct3, string opcodestr> :
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RVInstI<funct3, OPC_LOAD_FP, (outs VGPR:$rd),
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(ins VGPRMem:$rs1, simm12:$imm12),
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opcodestr # ".v" , "$rd, ${imm12}(${rs1})">, Sched<[]>;
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class VENTUS_VSWI12<bits<3> funct3, string opcodestr> :
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RVInstS<funct3, OPC_STORE_FP, (outs),
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(ins VGPR:$rs1, VGPRMem:$rs2, simm12:$imm12),
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opcodestr # ".v", "$rs1, ${imm12}(${rs2})">, Sched<[]>;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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@ -735,11 +744,15 @@ def VSUXEI32 : VectorStore<LSWidth32, "vsuxei32.v">;
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
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def VLW : RVInstSetVLi<1, (outs VGPR:$vd), (ins GPRMem:$rs1, simm11:$imm11),
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"vlw", "$vd, ${imm11}(${rs1})">;
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// FIXME: update funct3
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def VLWI12 : VENTUS_VLWI12<0b010, "vlw12">;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
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def VSW : RVInstSetVLi<0, (outs), (ins VGPR:$vd, GPRMem:$rs1, simm11:$imm11),
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"vsw", "$vd, ${imm11}(${rs1})">;
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// FIXME: update funct3
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def VSWI12 : VENTUS_VSWI12<0b010, "vsw12">;
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}
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let Predicates = [HasVInstructions] in {
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@ -1269,7 +1282,8 @@ def : DivergentNonPriStPat<store, VSUXEI32>;
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// Private memory per-thread load/store
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def : DivergentPriLdPat<load, VLW>;
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def : DivergentPriStPat<store, VSW>;
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def : DivergentPriLdPat<load, VLWI12>;
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def : DivergentPriStPat<store, VSWI12>;
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def DivergentSelectCCFrag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc,
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node:$truev, node:$falsev),
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