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Remove the MachineMove class. 

It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

llvm-svn: 181680
This commit is contained in:
Rafael Espindola 2013-05-13 01:16:13 +00:00
parent c6e16af2f4
commit 227144c23c
38 changed files with 169 additions and 177 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
llvm/include/llvm/CodeGen/AsmPrinter.h
View File

@ -38,8 +38,8 @@ namespace llvm {
class MachineConstantPoolValue;
class MachineJumpTableInfo;
class MachineModuleInfo;
class MachineMove;
class MCAsmInfo;
class MCCFIInstruction;
class MCContext;
class MCSection;
class MCStreamer;
@ -417,9 +417,8 @@ namespace llvm {
// Dwarf Lowering Routines
//===------------------------------------------------------------------===//
/// EmitCFIFrameMove - Emit frame instruction to describe the layout of the
/// frame.
void EmitCFIFrameMove(const MachineMove &Move) const;
/// \brief Emit frame instruction to describe the layout of the frame.
void emitCFIInstruction(const MCCFIInstruction &Inst) const;
//===------------------------------------------------------------------===//
// Inline Asm Support

16
llvm/include/llvm/CodeGen/MachineModuleInfo.h
View File

@ -106,9 +106,9 @@ class MachineModuleInfo : public ImmutablePass {
/// want.
MachineModuleInfoImpl *ObjFileMMI;
/// FrameMoves - List of moves done by a function's prolog. Used to construct
/// frame maps by debug and exception handling consumers.
std::vector<MachineMove> FrameMoves;
/// List of moves done by a function's prolog. Used to construct frame maps
/// by debug and exception handling consumers.
std::vector<MCCFIInstruction> FrameInstructions;
/// CompactUnwindEncoding - If the target supports it, this is the compact
/// unwind encoding. It replaces a function's CIE and FDE.
@ -231,15 +231,15 @@ public:
UsesVAFloatArgument = b;
}
/// getFrameMoves - Returns a reference to a list of moves done in the current
/// \brief Returns a reference to a list of cfi instructions in the current
/// function's prologue. Used to construct frame maps for debug and exception
/// handling comsumers.
const std::vector<MachineMove> &getFrameMoves() { return FrameMoves; }
const std::vector<MCCFIInstruction> &getFrameInstructions() {
return FrameInstructions;
}
void addFrameMove(MCSymbol *Label, const MachineLocation &Dst,
const MachineLocation &Src) {
FrameMoves.push_back(MachineMove(Label, Dst, Src));
}
const MachineLocation &Src);
/// getCompactUnwindEncoding - Returns the compact unwind encoding for a
/// function if the target supports the encoding. This encoding replaces a

11
llvm/include/llvm/MC/MCAsmInfo.h
View File

@ -17,6 +17,7 @@
#define LLVM_MC_MCASMINFO_H
#include "llvm/MC/MCDirectives.h"
#include "llvm/MC/MCDwarf.h"
#include "llvm/MC/MachineLocation.h"
#include <cassert>
#include <vector>
@ -332,7 +333,7 @@ namespace llvm {
//===--- Prologue State ----------------------------------------------===//
std::vector<MachineMove> InitialFrameState;
std::vector<MCCFIInstruction> InitialFrameState;
public:
explicit MCAsmInfo();
@ -567,11 +568,11 @@ namespace llvm {
return DwarfRegNumForCFI;
}
void addInitialFrameState(MCSymbol *label, const MachineLocation &D,
const MachineLocation &S) {
InitialFrameState.push_back(MachineMove(label, D, S));
void addInitialFrameState(const MCCFIInstruction &Inst) {
InitialFrameState.push_back(Inst);
}
const std::vector<MachineMove> &getInitialFrameState() const {
const std::vector<MCCFIInstruction> &getInitialFrameState() const {
return InitialFrameState;
}
};

29
llvm/include/llvm/MC/MachineLocation.h
View File

@ -10,11 +10,6 @@
// frame. Locations will be one of two forms; a register or an address formed
// from a base address plus an offset. Register indirection can be specified by
// explicitly passing an offset to the constructor.
//
// The MachineMove class is used to represent abstract move operations in the
// prolog/epilog of a compiled function. A collection of these objects can be
// used by a debug consumer to track the location of values when unwinding stack
// frames.
//===----------------------------------------------------------------------===//
@ -74,30 +69,6 @@ public:
void dump();
#endif
};
/// MachineMove - This class represents the save or restore of a callee saved
/// register that exception or debug info needs to know about.
class MachineMove {
private:
/// Label - Symbol for post-instruction address when result of move takes
/// effect.
MCSymbol *Label;
// Move to & from location.
MachineLocation Destination, Source;
public:
MachineMove() : Label(0) {}
MachineMove(MCSymbol *label, const MachineLocation &D,
const MachineLocation &S)
: Label(label), Destination(D), Source(S) {}
// Accessors
MCSymbol *getLabel() const { return Label; }
const MachineLocation &getDestination() const { return Destination; }
const MachineLocation &getSource() const { return Source; }
};
} // End llvm namespace
#endif

10
llvm/include/llvm/Support/TargetRegistry.h
View File

@ -70,7 +70,8 @@ namespace llvm {
typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);
typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(StringRef TT);
typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI,
StringRef TT);
typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
Reloc::Model RM,
CodeModel::Model CM,
@ -265,10 +266,11 @@ namespace llvm {
/// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
MCAsmInfo *createMCAsmInfo(StringRef Triple) const {
MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
StringRef Triple) const {
if (!MCAsmInfoCtorFn)
return 0;
return MCAsmInfoCtorFn(Triple);
return MCAsmInfoCtorFn(MRI, Triple);
}
/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
@ -803,7 +805,7 @@ namespace llvm {
TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
}
private:
static MCAsmInfo *Allocator(StringRef TT) {
static MCAsmInfo *Allocator(const MCRegisterInfo &MRI, StringRef TT) {
return new MCAsmInfoImpl(TT);
}

1
llvm/include/llvm/Target/TargetMachine.h
View File

@ -292,6 +292,7 @@ protected: // Can only create subclasses.
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
void initAsmInfo();
public:
/// \brief Register analysis passes for this target with a pass manager.
///

9
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -636,14 +636,13 @@ void AsmPrinter::emitPrologLabel(const MachineInstr &MI) {
OutStreamer.EmitCompactUnwindEncoding(MMI->getCompactUnwindEncoding());
MachineModuleInfo &MMI = MF->getMMI();
const std::vector<MachineMove> &Moves = MMI.getFrameMoves();
std::vector<MCCFIInstruction> Instructions = MMI.getFrameInstructions();
bool FoundOne = false;
(void)FoundOne;
for (std::vector<MachineMove>::const_iterator I = Moves.begin(),
E = Moves.end();
I != E; ++I) {
for (std::vector<MCCFIInstruction>::iterator I = Instructions.begin(),
E = Instructions.end(); I != E; ++I) {
if (I->getLabel() == Label) {
EmitCFIFrameMove(*I);
emitCFIInstruction(*I);
FoundOne = true;
}
}

39
llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
View File

@ -169,28 +169,21 @@ void AsmPrinter::EmitSectionOffset(const MCSymbol *Label,
// Dwarf Lowering Routines
//===----------------------------------------------------------------------===//
/// EmitCFIFrameMove - Emit a frame instruction.
void AsmPrinter::EmitCFIFrameMove(const MachineMove &Move) const {
const TargetRegisterInfo *RI = TM.getRegisterInfo();
const MachineLocation &Dst = Move.getDestination();
const MachineLocation &Src = Move.getSource();
// If advancing cfa.
if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
if (Src.getReg() == MachineLocation::VirtualFP) {
OutStreamer.EmitCFIDefCfaOffset(-Src.getOffset());
} else {
// Reg + Offset
OutStreamer.EmitCFIDefCfa(RI->getDwarfRegNum(Src.getReg(), true),
Src.getOffset());
}
} else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) {
assert(Dst.isReg() && "Machine move not supported yet.");
OutStreamer.EmitCFIDefCfaRegister(RI->getDwarfRegNum(Dst.getReg(), true));
} else {
assert(!Dst.isReg() && "Machine move not supported yet.");
OutStreamer.EmitCFIOffset(RI->getDwarfRegNum(Src.getReg(), true),
Dst.getOffset());
void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const {
switch (Inst.getOperation()) {
default:
llvm_unreachable("Unexpected instruction");
case MCCFIInstruction::OpDefCfaOffset:
OutStreamer.EmitCFIDefCfaOffset(Inst.getOffset());
break;
case MCCFIInstruction::OpDefCfa:
OutStreamer.EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset());
break;
case MCCFIInstruction::OpDefCfaRegister:
OutStreamer.EmitCFIDefCfaRegister(Inst.getRegister());
break;
case MCCFIInstruction::OpOffset:
OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset());
break;
}
}

1
llvm/lib/CodeGen/AsmPrinter/DwarfException.h
View File

@ -23,7 +23,6 @@ namespace llvm {
template <typename T> class SmallVectorImpl;
struct LandingPadInfo;
class MachineModuleInfo;
class MachineMove;
class MachineInstr;
class MachineFunction;
class MCAsmInfo;

19
llvm/lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -62,14 +62,8 @@ static bool getVerboseAsm() {
llvm_unreachable("Invalid verbose asm state");
}
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
StringRef CPU, StringRef FS,
TargetOptions Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: TargetMachine(T, Triple, CPU, FS, Options) {
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
AsmInfo = T.createMCAsmInfo(Triple);
void LLVMTargetMachine::initAsmInfo() {
AsmInfo = TheTarget.createMCAsmInfo(*getRegisterInfo(), TargetTriple);
// TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
// and if the old one gets included then MCAsmInfo will be NULL and
// we'll crash later.
@ -79,6 +73,15 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
"and that InitializeAllTargetMCs() is being invoked!");
}
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
StringRef CPU, StringRef FS,
TargetOptions Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: TargetMachine(T, Triple, CPU, FS, Options) {
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
}
void LLVMTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
PM.add(createBasicTargetTransformInfoPass(getTargetLowering()));
}

35
llvm/lib/CodeGen/MachineModuleInfo.cpp
View File

@ -268,6 +268,39 @@ MachineModuleInfo::MachineModuleInfo()
MachineModuleInfo::~MachineModuleInfo() {
}
static MCCFIInstruction convertMoveToCFI(const MCRegisterInfo &MRI,
MCSymbol *Label,
const MachineLocation &Dst,
const MachineLocation &Src) {
// If advancing cfa.
if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
if (Src.getReg() == MachineLocation::VirtualFP)
return MCCFIInstruction::createDefCfaOffset(Label, Src.getOffset());
// Reg + Offset
return MCCFIInstruction::createDefCfa(
Label, MRI.getDwarfRegNum(Src.getReg(), true), -Src.getOffset());
}
if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) {
assert(Dst.isReg() && "Machine move not supported yet.");
return MCCFIInstruction::createDefCfaRegister(
Label, MRI.getDwarfRegNum(Dst.getReg(), true));
}
assert(!Dst.isReg() && "Machine move not supported yet.");
return MCCFIInstruction::createOffset(
Label, MRI.getDwarfRegNum(Src.getReg(), true), Dst.getOffset());
}
void MachineModuleInfo::addFrameMove(MCSymbol *Label,
const MachineLocation &Dst,
const MachineLocation &Src) {
MCCFIInstruction I =
convertMoveToCFI(Context.getRegisterInfo(), Label, Dst, Src);
FrameInstructions.push_back(I);
}
bool MachineModuleInfo::doInitialization(Module &M) {
ObjFileMMI = 0;
@ -303,7 +336,7 @@ bool MachineModuleInfo::doFinalization(Module &M) {
///
void MachineModuleInfo::EndFunction() {
// Clean up frame info.
FrameMoves.clear();
FrameInstructions.clear();
// Clean up exception info.
LandingPads.clear();

10
llvm/lib/MC/MCDisassembler/Disassembler.cpp
View File

@ -42,8 +42,12 @@ LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *Triple, const char *CPU,
const Target *TheTarget = TargetRegistry::lookupTarget(Triple, Error);
assert(TheTarget && "Unable to create target!");
const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple);
if (!MRI)
return 0;
// Get the assembler info needed to setup the MCContext.
const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(Triple);
const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple);
if (!MAI)
return 0;
@ -51,10 +55,6 @@ LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *Triple, const char *CPU,
if (!MII)
return 0;
const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple);
if (!MRI)
return 0;
// Package up features to be passed to target/subtarget
std::string FeaturesStr;

39
llvm/lib/MC/MCDwarf.cpp
View File

@ -873,17 +873,6 @@ static void EmitPersonality(MCStreamer &streamer, const MCSymbol &symbol,
streamer.EmitValue(v, size);
}
static const MachineLocation TranslateMachineLocation(
const MCRegisterInfo &MRI,
const MachineLocation &Loc) {
unsigned Reg = Loc.getReg() == MachineLocation::VirtualFP ?
MachineLocation::VirtualFP :
unsigned(MRI.getDwarfRegNum(Loc.getReg(), true));
const MachineLocation &NewLoc = Loc.isReg() ?
MachineLocation(Reg) : MachineLocation(Reg, Loc.getOffset());
return NewLoc;
}
namespace {
class FrameEmitterImpl {
int CFAOffset;
@ -1316,32 +1305,8 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(MCStreamer &streamer,
// Initial Instructions
const MCAsmInfo &MAI = context.getAsmInfo();
const std::vector<MachineMove> &Moves = MAI.getInitialFrameState();
std::vector<MCCFIInstruction> Instructions;
for (int i = 0, n = Moves.size(); i != n; ++i) {
MCSymbol *Label = Moves[i].getLabel();
const MachineLocation &Dst =
TranslateMachineLocation(MRI, Moves[i].getDestination());
const MachineLocation &Src =
TranslateMachineLocation(MRI, Moves[i].getSource());
if (Dst.isReg()) {
assert(Dst.getReg() == MachineLocation::VirtualFP);
assert(!Src.isReg());
MCCFIInstruction Inst =
MCCFIInstruction::createDefCfa(Label, Src.getReg(), -Src.getOffset());
Instructions.push_back(Inst);
} else {
assert(Src.isReg());
unsigned Reg = Src.getReg();
int Offset = Dst.getOffset();
MCCFIInstruction Inst =
MCCFIInstruction::createOffset(Label, Reg, Offset);
Instructions.push_back(Inst);
}
}
const std::vector<MCCFIInstruction> &Instructions =
MAI.getInitialFrameState();
EmitCFIInstructions(streamer, Instructions, NULL);
// Padding

1
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -38,6 +38,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget) {
initAsmInfo();
}
namespace {

9
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
View File

@ -57,13 +57,14 @@ static MCRegisterInfo *createAArch64MCRegisterInfo(StringRef Triple) {
return X;
}
static MCAsmInfo *createAArch64MCAsmInfo(StringRef TT) {
static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
StringRef TT) {
Triple TheTriple(TT);
MCAsmInfo *MAI = new AArch64ELFMCAsmInfo();
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(AArch64::XSP, 0);
MAI->addInitialFrameState(0, Dst, Src);
unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0);
MAI->addInitialFrameState(Inst);
return MAI;
}

2
llvm/lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -85,6 +85,7 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget) {
initAsmInfo();
if (!Subtarget.hasARMOps())
report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
"support ARM mode execution!");
@ -117,6 +118,7 @@ ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
FrameLowering(Subtarget.hasThumb2()
? new ARMFrameLowering(Subtarget)
: (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
initAsmInfo();
}
namespace {

2
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -159,7 +159,7 @@ static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
return X;
}
static MCAsmInfo *createARMMCAsmInfo(StringRef TT) {
static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
Triple TheTriple(TT);
if (TheTriple.isOSDarwin())

1
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -79,6 +79,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
FrameLowering(Subtarget),
InstrItins(&Subtarget.getInstrItineraryData()) {
setMCUseCFI(false);
initAsmInfo();
}
// addPassesForOptimizations - Allow the backend (target) to add Target

9
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
View File

@ -54,13 +54,14 @@ static MCSubtargetInfo *createHexagonMCSubtargetInfo(StringRef TT,
return X;
}
static MCAsmInfo *createHexagonMCAsmInfo(StringRef TT) {
static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
StringRef TT) {
MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
// VirtualFP = (R30 + #0).
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(Hexagon::R30, 0);
MAI->addInitialFrameState(0, Dst, Src);
MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
0, Hexagon::R30, 0);
MAI->addInitialFrameState(Inst);
return MAI;
}

1
llvm/lib/Target/MBlaze/MBlazeTargetMachine.cpp
View File

@ -43,6 +43,7 @@ MBlazeTargetMachine(const Target &T, StringRef TT,
FrameLowering(Subtarget),
TLInfo(*this), TSInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
initAsmInfo();
}
namespace {

2
llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
View File

@ -53,7 +53,7 @@ static MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
return X;
}
static MCAsmInfo *createMCAsmInfo(StringRef TT) {
static MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
Triple TheTriple(TT);
switch (TheTriple.getOS()) {
default:

4
llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -36,7 +36,9 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T,
// FIXME: Check DataLayout string.
DL("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameLowering(Subtarget) { }
FrameLowering(Subtarget) {
initAsmInfo();
}
namespace {
/// MSP430 Code Generator Pass Configuration Options.

8
llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
View File

@ -93,12 +93,12 @@ static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
return X;
}
static MCAsmInfo *createMipsMCAsmInfo(StringRef TT) {
static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(Mips::SP, 0);
MAI->addInitialFrameState(0, Dst, Src);
unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, SP, 0);
MAI->addInitialFrameState(Inst);
return MAI;
}

1
llvm/lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -72,6 +72,7 @@ MipsTargetMachine(const Target &T, StringRef TT,
FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
TLInfo(MipsTargetLowering::create(*this)),
TSInfo(*this), JITInfo() {
initAsmInfo();
}

4
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@ -72,7 +72,9 @@ NVPTXTargetMachine::NVPTXTargetMachine(
Subtarget(TT, CPU, FS, is64bit), DL(Subtarget.getDataLayout()),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameLowering(
*this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {}
*this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
initAsmInfo();
}
void NVPTXTargetMachine32::anchor() {}

9
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -58,7 +58,7 @@ static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
return X;
}
static MCAsmInfo *createPPCMCAsmInfo(StringRef TT) {
static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
Triple TheTriple(TT);
bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
@ -69,9 +69,10 @@ static MCAsmInfo *createPPCMCAsmInfo(StringRef TT) {
MAI = new PPCLinuxMCAsmInfo(isPPC64);
// Initial state of the frame pointer is R1.
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(isPPC64? PPC::X1 : PPC::R1, 0);
MAI->addInitialFrameState(0, Dst, Src);
unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
MCCFIInstruction Inst =
MCCFIInstruction::createDefCfa(0, MRI.getDwarfRegNum(Reg, true), 0);
MAI->addInitialFrameState(Inst);
return MAI;
}

1
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -48,6 +48,7 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
// The binutils for the BG/P are too old for CFI.
if (Subtarget.isBGP())
setMCUseCFI(false);
initAsmInfo();
}
void PPC32TargetMachine::anchor() { }

1
llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@ -70,6 +70,7 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
InstrInfo = new SIInstrInfo(*this);
TLInfo = new SITargetLowering(*this);
}
initAsmInfo();
}
AMDGPUTargetMachine::~AMDGPUTargetMachine() {

1
llvm/lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -37,6 +37,7 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
InstrInfo(Subtarget),
TLInfo(*this), TSInfo(*this),
FrameLowering(Subtarget) {
initAsmInfo();
}
namespace {

10
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
View File

@ -27,11 +27,13 @@
using namespace llvm;
static MCAsmInfo *createSystemZMCAsmInfo(StringRef TT) {
static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
StringRef TT) {
MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
MachineLocation FPDst(MachineLocation::VirtualFP);
MachineLocation FPSrc(SystemZ::R15D, -SystemZMC::CFAOffsetFromInitialSP);
MAI->addInitialFrameState(0, FPDst, FPSrc);
MCCFIInstruction Inst =
MCCFIInstruction::createDefCfa(0, MRI.getDwarfRegNum(SystemZ::R15D, true),
SystemZMC::CFAOffsetFromInitialSP);
MAI->addInitialFrameState(Inst);
return MAI;
}

1
llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -33,6 +33,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
"-f32:32-f64:64-f128:64-a0:8:16-n32:64"),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameLowering(*this, Subtarget) {
initAsmInfo();
}
namespace {

16
llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -263,7 +263,7 @@ static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
return X;
}
static MCAsmInfo *createX86MCAsmInfo(StringRef TT) {
static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
Triple TheTriple(TT);
bool is64Bit = TheTriple.getArch() == Triple::x86_64;
@ -290,14 +290,16 @@ static MCAsmInfo *createX86MCAsmInfo(StringRef TT) {
int stackGrowth = is64Bit ? -8 : -4;
// Initial state of the frame pointer is esp+stackGrowth.
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
MAI->addInitialFrameState(0, Dst, Src);
unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
0, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
MAI->addInitialFrameState(Inst);
// Add return address to move list
MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
MAI->addInitialFrameState(0, CSDst, CSSrc);
unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
0, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
MAI->addInitialFrameState(Inst2);
return MAI;
}

2
llvm/lib/Target/X86/X86TargetMachine.cpp
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@ -49,6 +49,7 @@ X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
TLInfo(*this),
TSInfo(*this),
JITInfo(*this) {
initAsmInfo();
}
void X86_64TargetMachine::anchor() { }
@ -69,6 +70,7 @@ X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
TLInfo(*this),
TSInfo(*this),
JITInfo(*this) {
initAsmInfo();
}
/// X86TargetMachine ctor - Create an X86 target.

8
llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
View File

@ -51,13 +51,13 @@ static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU,
return X;
}
static MCAsmInfo *createXCoreMCAsmInfo(StringRef TT) {
static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
StringRef TT) {
MCAsmInfo *MAI = new XCoreMCAsmInfo(TT);
// Initial state of the frame pointer is SP.
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(XCore::SP, 0);
MAI->addInitialFrameState(0, Dst, Src);
MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, XCore::SP, 0);
MAI->addInitialFrameState(Inst);
return MAI;
}

1
llvm/lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -33,6 +33,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
FrameLowering(Subtarget),
TLInfo(*this),
TSInfo(*this) {
initAsmInfo();
}
namespace {

6
llvm/tools/llvm-mc/llvm-mc.cpp
View File

@ -379,12 +379,12 @@ int main(int argc, char **argv) {
// it later.
SrcMgr.setIncludeDirs(IncludeDirs);
llvm::OwningPtr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(TripleName));
assert(MAI && "Unable to create target asm info!");
llvm::OwningPtr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
assert(MRI && "Unable to create target register info!");
llvm::OwningPtr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
assert(MAI && "Unable to create target asm info!");
// FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and
// MCObjectFileInfo needs a MCContext reference in order to initialize itself.
OwningPtr<MCObjectFileInfo> MOFI(new MCObjectFileInfo());

5
llvm/tools/llvm-objdump/MachODump.cpp
View File

@ -251,11 +251,12 @@ static void DisassembleInputMachO2(StringRef Filename,
InstrAnalysis(TheTarget->createMCInstrAnalysis(InstrInfo.get()));
// Set up disassembler.
OwningPtr<const MCAsmInfo> AsmInfo(TheTarget->createMCAsmInfo(TripleName));
OwningPtr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
OwningPtr<const MCAsmInfo> AsmInfo(
TheTarget->createMCAsmInfo(*MRI, TripleName));
OwningPtr<const MCSubtargetInfo>
STI(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
OwningPtr<const MCDisassembler> DisAsm(TheTarget->createMCDisassembler(*STI));
OwningPtr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
OwningPtr<MCInstPrinter>
IP(TheTarget->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *InstrInfo,

15
llvm/tools/llvm-objdump/llvm-objdump.cpp
View File

@ -272,8 +272,15 @@ static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
if (Symbols.empty())
Symbols.push_back(std::make_pair(0, name));
OwningPtr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
if (!MRI) {
errs() << "error: no register info for target " << TripleName << "\n";
return;
}
// Set up disassembler.
OwningPtr<const MCAsmInfo> AsmInfo(TheTarget->createMCAsmInfo(TripleName));
OwningPtr<const MCAsmInfo> AsmInfo(
TheTarget->createMCAsmInfo(*MRI, TripleName));
if (!AsmInfo) {
errs() << "error: no assembly info for target " << TripleName << "\n";
@ -295,12 +302,6 @@ static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
return;
}
OwningPtr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
if (!MRI) {
errs() << "error: no register info for target " << TripleName << "\n";
return;
}
OwningPtr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo());
if (!MII) {
errs() << "error: no instruction info for target " << TripleName << "\n";