forked from OSchip/llvm-project
[PowerPC] Custom lower known CR bit spills
For known CRBit spills, CRSET/CRUNSET, it is more efficient to load and spill
the known value instead of extracting the bit.
eg. This sequence is currently used to spill a CRUNSET:
crclr 4*cr5+lt
mfocrf r3,4
rlwinm r3,r3,20,0,0
stw r3,132(r1)
This patch custom lower it to:
li r3,0
stw r3,132(r1)
Differential Revision: https://reviews.llvm.org/D61754
llvm-svn: 360677
This commit is contained in:
Lei Huang
parent
9e88a26863
commit
22561972af
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@ -70,6 +70,12 @@ StackPtrConst("ppc-stack-ptr-caller-preserved",
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"caller preserved registers can be LICM candidates"),
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"caller preserved registers can be LICM candidates"),
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cl::init(true), cl::Hidden);
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cl::init(true), cl::Hidden);
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static cl::opt<unsigned>
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MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
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cl::desc("Maximum search distance for definition of CR bit "
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"spill on ppc"),
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cl::Hidden, cl::init(100));
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static unsigned offsetMinAlignForOpcode(unsigned OpC);
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static unsigned offsetMinAlignForOpcode(unsigned OpC);
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PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
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PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
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@ -710,6 +716,7 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
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MachineFunction &MF = *MBB.getParent();
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MachineFunction &MF = *MBB.getParent();
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const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
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const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
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DebugLoc dl = MI.getDebugLoc();
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DebugLoc dl = MI.getDebugLoc();
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bool LP64 = TM.isPPC64();
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bool LP64 = TM.isPPC64();
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@ -719,27 +726,59 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
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unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
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unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
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unsigned SrcReg = MI.getOperand(0).getReg();
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unsigned SrcReg = MI.getOperand(0).getReg();
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// We need to move the CR field that contains the CR bit we are spilling.
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// Search up the BB to find the definition of the CR bit.
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// The super register may not be explicitly defined (i.e. it can be defined
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MachineBasicBlock::reverse_iterator Ins;
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// by a CR-logical that only defines the subreg) so we state that the CR
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unsigned CRBitSpillDistance = 0;
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// field is undef. Also, in order to preserve the kill flag on the CR bit,
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for (Ins = MI; Ins != MBB.rend(); Ins++) {
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// we add it as an implicit use.
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// Definition found.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
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if (Ins->modifiesRegister(SrcReg, TRI))
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break;
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// Unable to find CR bit definition within maximum search distance.
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if (CRBitSpillDistance == MaxCRBitSpillDist) {
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Ins = MI;
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break;
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}
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// Skip debug instructions when counting CR bit spill distance.
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if (!Ins->isDebugInstr())
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CRBitSpillDistance++;
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}
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// Unable to find the definition of the CR bit in the MBB.
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if (Ins == MBB.rend())
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Ins = MI;
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// There is no need to extract the CR bit if its value is already known.
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switch (Ins->getOpcode()) {
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case PPC::CRUNSET:
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg)
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.addImm(0);
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break;
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case PPC::CRSET:
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
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.addImm(-32768);
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break;
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default:
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// We need to move the CR field that contains the CR bit we are spilling.
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// The super register may not be explicitly defined (i.e. it can be defined
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// by a CR-logical that only defines the subreg) so we state that the CR
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// field is undef. Also, in order to preserve the kill flag on the CR bit,
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// we add it as an implicit use.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
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.addReg(getCRFromCRBit(SrcReg), RegState::Undef)
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.addReg(getCRFromCRBit(SrcReg), RegState::Undef)
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.addReg(SrcReg,
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.addReg(SrcReg,
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RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
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RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
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// If the saved register wasn't CR0LT, shift the bits left so that the bit to
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// If the saved register wasn't CR0LT, shift the bits left so that the bit
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// store is the first one. Mask all but that bit.
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// to store is the first one. Mask all but that bit.
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unsigned Reg1 = Reg;
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unsigned Reg1 = Reg;
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Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
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Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
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// rlwinm rA, rA, ShiftBits, 0, 0.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
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.addReg(Reg1, RegState::Kill)
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.addImm(getEncodingValue(SrcReg))
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.addImm(0).addImm(0);
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// rlwinm rA, rA, ShiftBits, 0, 0.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
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.addReg(Reg1, RegState::Kill)
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.addImm(getEncodingValue(SrcReg))
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.addImm(0).addImm(0);
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}
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addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
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addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
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.addReg(Reg, RegState::Kill),
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.addReg(Reg, RegState::Kill),
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FrameIndex);
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FrameIndex);
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@ -0,0 +1,131 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; For known CRBit spills, CRSET/CRUNSET, it is more efficient to just load and
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; spill the known value. These tests verify that for CRSET and CRUNSET spills
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; we do not extract the bit for spilling.
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%struct.anon = type { i32 }
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@b = common dso_local global %struct.anon* null, align 8
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@a = common dso_local global i64 0, align 8
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; Function Attrs: nounwind
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define dso_local signext i32 @spillCRSET(i32 signext %p1, i32 signext %p2) {
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; CHECK-LABEL: spillCRSET:
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; CHECK: # %bb.0: # %entry
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; CHECK: lis [[REG1:.*]], -32768
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; CHECK-DAG: creqv [[CREG:.*]]*cr5+lt, [[CREG]]*cr5+lt, [[CREG]]*cr5+lt
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; CHECK-NOT: mfocrf [[REG2:.*]], [[CREG]]
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; CHECK-NOT: rlwinm [[REG2]], [[REG2]]
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; CHECK: stw [[REG1]]
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; CHECK: .LBB0_1: # %redo_first_pass
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entry:
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%tobool = icmp eq i32 %p2, 0
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%tobool2 = icmp eq i32 %p1, 0
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br label %redo_first_pass
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redo_first_pass: ; preds = %for.end, %entry
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %redo_first_pass
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%call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 ()*)() #2
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%tobool1 = icmp ne i32 %call, 0
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br label %if.end
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if.end: ; preds = %redo_first_pass, %if.then
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%c.1.off0 = phi i1 [ %tobool1, %if.then ], [ true, %redo_first_pass ]
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br i1 %tobool2, label %if.end4, label %if.then3
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if.then3: ; preds = %if.end
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%0 = load %struct.anon*, %struct.anon** @b, align 8
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%contains_i = getelementptr inbounds %struct.anon, %struct.anon* %0, i64 0, i32 0
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store i32 1, i32* %contains_i, align 4
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br label %if.end4
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if.end4: ; preds = %if.end, %if.then3
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tail call void asm sideeffect "#DO_NOTHING", "~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}"()
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br i1 %c.1.off0, label %if.then6, label %if.end13
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if.then6: ; preds = %if.end4
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%1 = load i64, i64* @a, align 8
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%cmp21 = icmp eq i64 %1, 0
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br i1 %cmp21, label %if.end13, label %for.body
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for.body: ; preds = %if.then6, %for.body
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%s.122 = phi i64 [ %inc, %for.body ], [ 0, %if.then6 ]
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%call7 = tail call signext i32 bitcast (i32 (...)* @fn3 to i32 ()*)()
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%inc = add nuw i64 %s.122, 1
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%exitcond = icmp eq i64 %inc, %1
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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br i1 %cmp21, label %if.end13, label %redo_first_pass
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if.end13: ; preds = %if.then6, %for.end, %if.end4
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ret i32 0
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}
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%struct.p5rx = type { i32 }
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; Function Attrs: nounwind
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define dso_local signext i32 @spillCRUNSET(%struct.p5rx* readonly %p1, i32 signext %p2, i32 signext %p3) {
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; CHECK-LABEL: spillCRUNSET:
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; CHECK: # %bb.0: # %entry
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; CHECK-DAG: crxor [[CREG:.*]]*cr5+lt, [[CREG]]*cr5+lt, [[CREG]]*cr5+lt
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; CHECK-DAG: li [[REG1:.*]], 0
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; CHECK-NOT: mfocrf [[REG2:.*]], [[CREG]]
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; CHECK-NOT: rlwinm [[REG2]], [[REG2]]
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; CHECK: stw [[REG1]]
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; CHECK: .LBB1_1: # %redo_first_pass
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entry:
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%and = and i32 %p3, 128
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%tobool = icmp eq i32 %and, 0
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%tobool2 = icmp eq %struct.p5rx* %p1, null
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%sv_any = getelementptr inbounds %struct.p5rx, %struct.p5rx* %p1, i64 0, i32 0
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%tobool12 = icmp eq i32 %p2, 0
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br label %redo_first_pass
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redo_first_pass: ; preds = %if.end11, %entry
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%a.0.off0 = phi i1 [ false, %entry ], [ %a.1.off0, %if.end11 ]
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %redo_first_pass
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%call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 ()*)()
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%tobool1 = icmp ne i32 %call, 0
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br label %if.end
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if.end: ; preds = %redo_first_pass, %if.then
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%a.1.off0 = phi i1 [ %tobool1, %if.then ], [ %a.0.off0, %redo_first_pass ]
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tail call void asm sideeffect "#DO_NOTHING", "~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}"()
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br i1 %tobool2, label %if.end11, label %land.lhs.true
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land.lhs.true: ; preds = %if.end
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%call3 = tail call signext i32 bitcast (i32 (...)* @fn3 to i32 ()*)()
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%tobool4 = icmp eq i32 %call3, 0
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br i1 %tobool4, label %if.end11, label %land.lhs.true5
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land.lhs.true5: ; preds = %land.lhs.true
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%0 = load i32, i32* %sv_any, align 4
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%tobool6 = icmp eq i32 %0, 0
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%a.1.off0.not = xor i1 %a.1.off0, true
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%brmerge = or i1 %tobool6, %a.1.off0.not
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br i1 %brmerge, label %if.end11, label %if.then9
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if.then9: ; preds = %land.lhs.true5
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%call10 = tail call signext i32 bitcast (i32 (...)* @fn4 to i32 ()*)()
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br label %if.end11
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if.end11: ; preds = %land.lhs.true5, %land.lhs.true, %if.end, %if.then9
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br i1 %tobool12, label %if.end14, label %redo_first_pass
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if.end14: ; preds = %if.end11
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ret i32 0
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}
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declare signext i32 @fn2(...)
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declare signext i32 @fn3(...)
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declare signext i32 @fn4(...)
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