forked from OSchip/llvm-project
[ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr
Summary: This enables clustering for many more BUF instructions. Reviewers: rampitec, arsenm, nhaehnle Subscribers: jvesely, wdng, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73868
This commit is contained in:
Jay Foad
parent
2ddff6fab0
commit
2252cac694
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@ -337,13 +337,15 @@ bool SIInstrInfo::getMemOperandsWithOffset(
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return true;
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}
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BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
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if (!BaseOp)
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BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
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if (!BaseOp) // e.g. BUFFER_WBINVL1_VOL
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return false;
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const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
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BaseOps.push_back(RSrc);
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BaseOps.push_back(BaseOp);
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BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
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if (BaseOp)
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BaseOps.push_back(BaseOp);
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const MachineOperand *OffsetImm =
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getNamedOperand(LdSt, AMDGPU::OpName::offset);
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Offset = OffsetImm->getImm();
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@ -668,7 +668,7 @@ define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i
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; VI-NEXT: s_lshl_b32 s6, s6, 8
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; VI-NEXT: s_or_b32 s4, s6, s4
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; VI-NEXT: v_or_b32_e32 v1, v1, v3
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; VI-NEXT: v_or_b32_e32 v5, s4, v1
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; VI-NEXT: v_or_b32_e32 v6, s4, v1
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; VI-NEXT: v_mov_b32_e32 v1, s8
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; VI-NEXT: v_alignbit_b32 v3, s9, v1, 24
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; VI-NEXT: v_alignbit_b32 v1, s9, v1, 8
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@ -678,11 +678,11 @@ define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i
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; VI-NEXT: v_and_b32_e32 v1, s17, v1
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; VI-NEXT: s_lshr_b32 s4, s9, 24
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; VI-NEXT: s_lshl_b32 s6, s6, 8
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; VI-NEXT: s_and_b32 s13, s15, s18
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; VI-NEXT: s_lshl_b64 s[14:15], s[10:11], 24
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; VI-NEXT: v_or_b32_e32 v1, v1, v3
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; VI-NEXT: s_or_b32 s4, s6, s4
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; VI-NEXT: v_or_b32_e32 v3, s4, v1
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; VI-NEXT: s_and_b32 s13, s15, s18
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; VI-NEXT: s_lshl_b64 s[14:15], s[10:11], 24
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; VI-NEXT: v_or_b32_e32 v4, s4, v1
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; VI-NEXT: s_lshl_b32 s4, s10, 8
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; VI-NEXT: s_and_b32 s15, s15, s19
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; VI-NEXT: s_mov_b32 s14, s12
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@ -704,11 +704,11 @@ define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i
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; VI-NEXT: s_mov_b32 s8, s12
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; VI-NEXT: s_or_b64 s[8:9], s[12:13], s[8:9]
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; VI-NEXT: s_or_b64 s[8:9], s[8:9], s[14:15]
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; VI-NEXT: v_mov_b32_e32 v4, s9
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; VI-NEXT: v_mov_b32_e32 v6, s11
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; VI-NEXT: buffer_store_dwordx4 v[3:6], off, s[0:3], 0 offset:16
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; VI-NEXT: v_mov_b32_e32 v5, s9
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; VI-NEXT: v_mov_b32_e32 v7, s11
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; VI-NEXT: v_mov_b32_e32 v1, s5
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; VI-NEXT: v_mov_b32_e32 v3, s7
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; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
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; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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; VI-NEXT: s_endpgm
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%val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
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@ -437,9 +437,9 @@ define amdgpu_kernel void @test_copy_v3i8_align4(<3 x i8> addrspace(1)* %out, <3
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; VI-NEXT: s_mov_b32 s4, s0
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; VI-NEXT: s_mov_b32 s5, s1
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; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
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; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
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; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0 offset:2
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; VI-NEXT: buffer_store_byte v1, off, s[4:7], 0 offset:2
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; VI-NEXT: s_endpgm
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%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %in, i32 %tid.x
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@ -172,13 +172,19 @@ define amdgpu_kernel void @v_cttz_zero_undef_i32_with_select(i32 addrspace(1)* n
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; SI-NOSDWA: v_or_b32_e32
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; SI-NOSDWA: v_or_b32_e32
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; SI-NOSDWA: v_or_b32_e32
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; SI-SDWA: v_or_b32_sdwa
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; SI-NOSDWA: v_or_b32_e32
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; SI-NOSDWA: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; SI-NOSDWA: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]]
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; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]]
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; SI-SDWA: v_or_b32_e32
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; SI-SDWA: v_or_b32_sdwa
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; SI: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; SI: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; SI-DAG: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]]
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; SI-DAG: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]]
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; SI-SDWA: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; SI-SDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]]
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; SI-SDWA: v_or_b32_e32
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; SI-SDWA: v_or_b32_sdwa
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; SI-SDWA: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; SI-SDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]]
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; SI: v_cmp_eq_u32_e32 vcc, 0
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; SI: v_cmp_ne_u64_e32 vcc, 0
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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@ -365,35 +365,34 @@ define amdgpu_kernel void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias
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; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64
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; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1
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; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:2
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; SI-NEXT: buffer_load_ubyte v5, v[0:1], s[0:3], 0 addr64 offset:3
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; SI-NEXT: buffer_load_ubyte v6, v[0:1], s[0:3], 0 addr64 offset:4
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; SI-NEXT: buffer_load_ubyte v7, v[0:1], s[0:3], 0 addr64 offset:5
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; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:6
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; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64 offset:5
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; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:6
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; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64
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; SI-NEXT: buffer_load_ubyte v5, v[0:1], s[0:3], 0 addr64 offset:1
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; SI-NEXT: buffer_load_ubyte v6, v[0:1], s[0:3], 0 addr64 offset:2
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; SI-NEXT: buffer_load_ubyte v7, v[0:1], s[0:3], 0 addr64 offset:3
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; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:4
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_waitcnt vmcnt(5)
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; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v3
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; SI-NEXT: v_or_b32_e32 v1, v1, v2
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; SI-NEXT: s_waitcnt vmcnt(6)
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; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
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; SI-NEXT: s_waitcnt vmcnt(3)
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; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
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; SI-NEXT: v_or_b32_e32 v2, v2, v4
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; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
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; SI-NEXT: v_or_b32_e32 v1, v1, v4
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; SI-NEXT: s_waitcnt vmcnt(1)
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; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v7
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; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v7
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; SI-NEXT: v_cvt_f32_ubyte0_e32 v7, v3
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; SI-NEXT: v_or_b32_e32 v3, v5, v6
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
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; SI-NEXT: v_or_b32_e32 v3, v3, v6
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:24
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; SI-NEXT: s_waitcnt expcnt(0)
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; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
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; SI-NEXT: v_or_b32_e32 v0, v0, v1
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; SI-NEXT: v_cvt_f32_ubyte1_e32 v5, v3
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; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v3
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; SI-NEXT: v_or_b32_e32 v0, v2, v0
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; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
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; SI-NEXT: v_cvt_f32_ubyte1_e32 v5, v0
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; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v0
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; SI-NEXT: v_or_b32_e32 v0, v2, v1
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; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
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; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
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; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
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; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
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; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:24
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; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[4:7], 0 offset:16
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; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
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; SI-NEXT: s_endpgm
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@ -911,9 +911,9 @@ define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %
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; SI-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
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; SI-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
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; SI-NEXT: v_mov_b32_e32 v0, s5
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; SI-NEXT: v_mov_b32_e32 v1, s4
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; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: dynamic_insertelement_v3i16:
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@ -348,7 +348,7 @@ define amdgpu_kernel void @test_memcpy_const_string_align4(i8 addrspace(1)* noal
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; FUNC-LABEL: {{^}}test_memcpy_const_string_align1:
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; SI-NOT: buffer_load
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; SI: v_mov_b32_e32 v{{[0-9]+}}, 0x69
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; SI: v_mov_b32_e32 v{{[0-9]+}}, 0x
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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@ -529,8 +529,8 @@ define amdgpu_kernel void @merge_local_store_4_constants_i32(i32 addrspace(3)* %
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; GCN-LABEL: {{^}}merge_global_store_5_constants_i32:
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; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 9{{$}}
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; GCN-DAG: v_mov_b32_e32 v[[HI4:[0-9]+]], -12{{$}}
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; GCN: buffer_store_dwordx4 v{{\[}}[[LO]]:[[HI4]]{{\]}}
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; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 11{{$}}
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; GCN: buffer_store_dwordx4 v{{\[}}[[LO]]:[[HI4]]{{\]}}
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; GCN: buffer_store_dword v[[HI]]
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define amdgpu_kernel void @merge_global_store_5_constants_i32(i32 addrspace(1)* %out) {
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store i32 9, i32 addrspace(1)* %out, align 4
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@ -1002,16 +1002,16 @@ define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> ad
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; TONGA-NEXT: s_waitcnt lgkmcnt(0)
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; TONGA-NEXT: s_mov_b32 s0, s14
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; TONGA-NEXT: s_mov_b32 s1, s15
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; TONGA-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
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; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
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; TONGA-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
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; TONGA-NEXT: s_mov_b32 s14, 0x4f800000
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; TONGA-NEXT: s_mov_b32 s8, s12
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; TONGA-NEXT: s_mov_b32 s9, s13
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; TONGA-NEXT: s_waitcnt vmcnt(1)
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; TONGA-NEXT: v_ashrrev_i32_e32 v8, 31, v0
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; TONGA-NEXT: s_waitcnt vmcnt(0)
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; TONGA-NEXT: v_ashrrev_i32_e32 v9, 31, v4
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; TONGA-NEXT: v_add_u32_e32 v4, vcc, v9, v4
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; TONGA-NEXT: s_waitcnt vmcnt(0)
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; TONGA-NEXT: v_ashrrev_i32_e32 v8, 31, v0
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; TONGA-NEXT: v_xor_b32_e32 v4, v4, v9
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; TONGA-NEXT: v_xor_b32_e32 v15, v8, v9
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; TONGA-NEXT: v_cvt_f32_u32_e32 v9, v4
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@ -1150,15 +1150,15 @@ define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> ad
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_mov_b32 s0, s10
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; GFX9-NEXT: s_mov_b32 s1, s11
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; GFX9-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
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; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
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; GFX9-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
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; GFX9-NEXT: s_mov_b32 s4, 0x4f800000
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; GFX9-NEXT: s_mov_b32 s12, s8
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; GFX9-NEXT: s_mov_b32 s13, s9
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; GFX9-NEXT: s_waitcnt vmcnt(1)
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; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v4
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v0
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v4
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; GFX9-NEXT: v_add_u32_e32 v4, v4, v9
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v8
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; GFX9-NEXT: v_xor_b32_e32 v4, v4, v9
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@ -1614,30 +1614,30 @@ define amdgpu_kernel void @v_sdiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %i
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; TONGA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; TONGA-NEXT: s_mov_b32 s3, 0xf000
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; TONGA-NEXT: s_mov_b32 s2, -1
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; TONGA-NEXT: s_mov_b32 s10, s2
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; TONGA-NEXT: s_mov_b32 s11, s3
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; TONGA-NEXT: s_waitcnt lgkmcnt(0)
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; TONGA-NEXT: s_mov_b32 s8, s6
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; TONGA-NEXT: s_mov_b32 s9, s7
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; TONGA-NEXT: buffer_load_sbyte v0, off, s[8:11], 0
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; TONGA-NEXT: buffer_load_sbyte v1, off, s[8:11], 0 offset:1
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; TONGA-NEXT: s_mov_b32 s0, s4
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; TONGA-NEXT: s_mov_b32 s1, s5
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; TONGA-NEXT: s_mov_b32 s4, s6
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; TONGA-NEXT: s_mov_b32 s5, s7
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; TONGA-NEXT: s_mov_b32 s6, s2
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; TONGA-NEXT: s_mov_b32 s7, s3
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; TONGA-NEXT: buffer_load_sbyte v0, off, s[4:7], 0 offset:1
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; TONGA-NEXT: buffer_load_sbyte v2, off, s[4:7], 0
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; TONGA-NEXT: s_waitcnt vmcnt(1)
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; TONGA-NEXT: v_cvt_f32_i32_e32 v1, v0
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; TONGA-NEXT: v_cvt_f32_i32_e32 v3, v0
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; TONGA-NEXT: s_waitcnt vmcnt(0)
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; TONGA-NEXT: v_cvt_f32_i32_e32 v3, v2
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; TONGA-NEXT: v_xor_b32_e32 v0, v2, v0
|
||||
; TONGA-NEXT: v_cvt_f32_i32_e32 v2, v1
|
||||
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v1
|
||||
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 30, v0
|
||||
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v1
|
||||
; TONGA-NEXT: v_or_b32_e32 v0, 1, v0
|
||||
; TONGA-NEXT: v_mul_f32_e32 v2, v3, v4
|
||||
; TONGA-NEXT: v_trunc_f32_e32 v2, v2
|
||||
; TONGA-NEXT: v_mad_f32 v3, -v2, v1, v3
|
||||
; TONGA-NEXT: v_cvt_i32_f32_e32 v2, v2
|
||||
; TONGA-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
|
||||
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v2
|
||||
; TONGA-NEXT: v_mul_f32_e32 v1, v3, v4
|
||||
; TONGA-NEXT: v_trunc_f32_e32 v1, v1
|
||||
; TONGA-NEXT: v_mad_f32 v3, -v1, v2, v3
|
||||
; TONGA-NEXT: v_cvt_i32_f32_e32 v1, v1
|
||||
; TONGA-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
|
||||
; TONGA-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
|
||||
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
||||
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v1
|
||||
; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 8
|
||||
; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; TONGA-NEXT: s_endpgm
|
||||
|
|
@ -1647,28 +1647,28 @@ define amdgpu_kernel void @v_sdiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %i
|
|||
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GFX9-NEXT: s_mov_b32 s2, -1
|
||||
; GFX9-NEXT: s_mov_b32 s10, s2
|
||||
; GFX9-NEXT: s_mov_b32 s11, s3
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: s_mov_b32 s8, s6
|
||||
; GFX9-NEXT: s_mov_b32 s9, s7
|
||||
; GFX9-NEXT: buffer_load_sbyte v0, off, s[8:11], 0
|
||||
; GFX9-NEXT: buffer_load_sbyte v1, off, s[8:11], 0 offset:1
|
||||
; GFX9-NEXT: s_mov_b32 s0, s4
|
||||
; GFX9-NEXT: s_mov_b32 s1, s5
|
||||
; GFX9-NEXT: s_mov_b32 s4, s6
|
||||
; GFX9-NEXT: s_mov_b32 s5, s7
|
||||
; GFX9-NEXT: s_mov_b32 s6, s2
|
||||
; GFX9-NEXT: s_mov_b32 s7, s3
|
||||
; GFX9-NEXT: buffer_load_sbyte v0, off, s[4:7], 0 offset:1
|
||||
; GFX9-NEXT: buffer_load_sbyte v2, off, s[4:7], 0
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
||||
; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v0
|
||||
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v0
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v2
|
||||
; GFX9-NEXT: v_xor_b32_e32 v0, v2, v0
|
||||
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v1
|
||||
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
|
||||
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0
|
||||
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v1
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
|
||||
; GFX9-NEXT: v_mul_f32_e32 v2, v3, v4
|
||||
; GFX9-NEXT: v_trunc_f32_e32 v2, v2
|
||||
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v2
|
||||
; GFX9-NEXT: v_mad_f32 v2, -v2, v1, v3
|
||||
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
|
||||
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v2
|
||||
; GFX9-NEXT: v_mul_f32_e32 v1, v3, v4
|
||||
; GFX9-NEXT: v_trunc_f32_e32 v1, v1
|
||||
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v1
|
||||
; GFX9-NEXT: v_mad_f32 v1, -v1, v2, v3
|
||||
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2|
|
||||
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
|
||||
; GFX9-NEXT: v_add_u32_e32 v0, v4, v0
|
||||
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 8
|
||||
|
|
@ -1729,14 +1729,14 @@ define amdgpu_kernel void @v_sdiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)*
|
|||
; GCN-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:2
|
||||
; GCN-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:6
|
||||
; GCN-NEXT: buffer_load_ushort v0, off, s[8:11], 0
|
||||
; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4
|
||||
; GCN-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-NEXT: s_waitcnt vmcnt(3)
|
||||
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; GCN-NEXT: s_waitcnt vmcnt(2)
|
||||
|
|
@ -1776,32 +1776,31 @@ define amdgpu_kernel void @v_sdiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)*
|
|||
; TONGA-NEXT: s_mov_b32 s5, s7
|
||||
; TONGA-NEXT: s_mov_b32 s6, s2
|
||||
; TONGA-NEXT: s_mov_b32 s7, s3
|
||||
; TONGA-NEXT: buffer_load_ubyte v0, off, s[4:7], 0 offset:2
|
||||
; TONGA-NEXT: buffer_load_ushort v1, off, s[4:7], 0 offset:4
|
||||
; TONGA-NEXT: buffer_load_ubyte v2, off, s[4:7], 0 offset:6
|
||||
; TONGA-NEXT: buffer_load_ushort v3, off, s[4:7], 0
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(3)
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(1)
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
||||
; TONGA-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; TONGA-NEXT: v_bfe_i32 v1, v1, 0, 23
|
||||
; TONGA-NEXT: v_cvt_f32_i32_e32 v2, v1
|
||||
; TONGA-NEXT: buffer_load_ushort v0, off, s[4:7], 0
|
||||
; TONGA-NEXT: buffer_load_ubyte v1, off, s[4:7], 0 offset:2
|
||||
; TONGA-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4
|
||||
; TONGA-NEXT: buffer_load_ubyte v3, off, s[4:7], 0 offset:6
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(2)
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; TONGA-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(0)
|
||||
; TONGA-NEXT: v_or_b32_e32 v0, v3, v0
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
||||
; TONGA-NEXT: v_or_b32_e32 v2, v2, v3
|
||||
; TONGA-NEXT: v_bfe_i32 v2, v2, 0, 23
|
||||
; TONGA-NEXT: v_cvt_f32_i32_e32 v3, v2
|
||||
; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 23
|
||||
; TONGA-NEXT: v_cvt_f32_i32_e32 v3, v0
|
||||
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v2
|
||||
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v1
|
||||
; TONGA-NEXT: v_cvt_f32_i32_e32 v1, v0
|
||||
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v2
|
||||
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v3
|
||||
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 30, v0
|
||||
; TONGA-NEXT: v_or_b32_e32 v0, 1, v0
|
||||
; TONGA-NEXT: v_mul_f32_e32 v1, v3, v4
|
||||
; TONGA-NEXT: v_trunc_f32_e32 v1, v1
|
||||
; TONGA-NEXT: v_mad_f32 v3, -v1, v2, v3
|
||||
; TONGA-NEXT: v_cvt_i32_f32_e32 v1, v1
|
||||
; TONGA-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
|
||||
; TONGA-NEXT: v_mul_f32_e32 v2, v1, v4
|
||||
; TONGA-NEXT: v_trunc_f32_e32 v2, v2
|
||||
; TONGA-NEXT: v_mad_f32 v1, -v2, v3, v1
|
||||
; TONGA-NEXT: v_cvt_i32_f32_e32 v2, v2
|
||||
; TONGA-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3|
|
||||
; TONGA-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
|
||||
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v1
|
||||
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
||||
; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 23
|
||||
; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; TONGA-NEXT: s_endpgm
|
||||
|
|
@ -1818,30 +1817,29 @@ define amdgpu_kernel void @v_sdiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)*
|
|||
; GFX9-NEXT: s_mov_b32 s5, s7
|
||||
; GFX9-NEXT: s_mov_b32 s6, s2
|
||||
; GFX9-NEXT: s_mov_b32 s7, s3
|
||||
; GFX9-NEXT: buffer_load_ubyte v0, off, s[4:7], 0 offset:2
|
||||
; GFX9-NEXT: buffer_load_ushort v1, off, s[4:7], 0 offset:4
|
||||
; GFX9-NEXT: buffer_load_ubyte v2, off, s[4:7], 0 offset:6
|
||||
; GFX9-NEXT: buffer_load_ushort v3, off, s[4:7], 0
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(3)
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
||||
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 23
|
||||
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v1
|
||||
; GFX9-NEXT: buffer_load_ushort v0, off, s[4:7], 0
|
||||
; GFX9-NEXT: buffer_load_ubyte v1, off, s[4:7], 0 offset:2
|
||||
; GFX9-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4
|
||||
; GFX9-NEXT: buffer_load_ubyte v3, off, s[4:7], 0 offset:6
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
||||
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
|
||||
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 23
|
||||
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v2
|
||||
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 23
|
||||
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v0
|
||||
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v2
|
||||
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
|
||||
; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v0
|
||||
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
|
||||
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v3
|
||||
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
|
||||
; GFX9-NEXT: v_mul_f32_e32 v1, v3, v4
|
||||
; GFX9-NEXT: v_trunc_f32_e32 v1, v1
|
||||
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v1
|
||||
; GFX9-NEXT: v_mad_f32 v1, -v1, v2, v3
|
||||
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2|
|
||||
; GFX9-NEXT: v_mul_f32_e32 v2, v1, v4
|
||||
; GFX9-NEXT: v_trunc_f32_e32 v2, v2
|
||||
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v2
|
||||
; GFX9-NEXT: v_mad_f32 v1, -v2, v3, v1
|
||||
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3|
|
||||
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
|
||||
; GFX9-NEXT: v_add_u32_e32 v0, v4, v0
|
||||
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 23
|
||||
|
|
@ -1916,14 +1914,14 @@ define amdgpu_kernel void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)*
|
|||
; GCN-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-NEXT: buffer_load_sbyte v1, off, s[8:11], 0 offset:2
|
||||
; GCN-NEXT: buffer_load_sbyte v3, off, s[8:11], 0 offset:6
|
||||
; GCN-NEXT: buffer_load_ushort v0, off, s[8:11], 0
|
||||
; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4
|
||||
; GCN-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-NEXT: s_waitcnt vmcnt(3)
|
||||
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; GCN-NEXT: s_waitcnt vmcnt(2)
|
||||
|
|
@ -1961,30 +1959,29 @@ define amdgpu_kernel void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)*
|
|||
; TONGA-NEXT: s_mov_b32 s5, s7
|
||||
; TONGA-NEXT: s_mov_b32 s6, s2
|
||||
; TONGA-NEXT: s_mov_b32 s7, s3
|
||||
; TONGA-NEXT: buffer_load_sbyte v0, off, s[4:7], 0 offset:2
|
||||
; TONGA-NEXT: buffer_load_ushort v1, off, s[4:7], 0 offset:4
|
||||
; TONGA-NEXT: buffer_load_sbyte v2, off, s[4:7], 0 offset:6
|
||||
; TONGA-NEXT: buffer_load_ushort v3, off, s[4:7], 0
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(3)
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(1)
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
||||
; TONGA-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; TONGA-NEXT: v_cvt_f32_i32_e32 v1, v1
|
||||
; TONGA-NEXT: buffer_load_ushort v0, off, s[4:7], 0
|
||||
; TONGA-NEXT: buffer_load_sbyte v1, off, s[4:7], 0 offset:2
|
||||
; TONGA-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4
|
||||
; TONGA-NEXT: buffer_load_sbyte v3, off, s[4:7], 0 offset:6
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(2)
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; TONGA-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(0)
|
||||
; TONGA-NEXT: v_or_b32_e32 v3, v3, v0
|
||||
; TONGA-NEXT: v_cvt_f32_i32_e32 v3, v3
|
||||
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v2
|
||||
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v1
|
||||
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 30, v0
|
||||
; TONGA-NEXT: v_or_b32_e32 v0, 1, v0
|
||||
; TONGA-NEXT: v_mul_f32_e32 v2, v3, v4
|
||||
; TONGA-NEXT: v_trunc_f32_e32 v2, v2
|
||||
; TONGA-NEXT: v_mad_f32 v3, -v2, v1, v3
|
||||
; TONGA-NEXT: v_cvt_i32_f32_e32 v2, v2
|
||||
; TONGA-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
|
||||
; TONGA-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
|
||||
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
||||
; TONGA-NEXT: v_or_b32_e32 v2, v2, v3
|
||||
; TONGA-NEXT: v_cvt_f32_i32_e32 v2, v2
|
||||
; TONGA-NEXT: v_cvt_f32_i32_e32 v0, v0
|
||||
; TONGA-NEXT: v_xor_b32_e32 v1, v1, v3
|
||||
; TONGA-NEXT: v_ashrrev_i32_e32 v1, 30, v1
|
||||
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v2
|
||||
; TONGA-NEXT: v_or_b32_e32 v1, 1, v1
|
||||
; TONGA-NEXT: v_mul_f32_e32 v3, v0, v4
|
||||
; TONGA-NEXT: v_trunc_f32_e32 v3, v3
|
||||
; TONGA-NEXT: v_mad_f32 v0, -v3, v2, v0
|
||||
; TONGA-NEXT: v_cvt_i32_f32_e32 v3, v3
|
||||
; TONGA-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v2|
|
||||
; TONGA-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
|
||||
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v3
|
||||
; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 24
|
||||
; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; TONGA-NEXT: s_endpgm
|
||||
|
|
|
|||
|
|
@ -415,18 +415,18 @@ define amdgpu_kernel void @shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> add
|
|||
; GCN-NEXT: s_mov_b32 s14, 0
|
||||
; GCN-NEXT: s_mov_b32 s15, s7
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], s[2:3]
|
||||
; GCN-NEXT: buffer_load_dword v2, off, s[8:11], 0
|
||||
; GCN-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64 offset:4
|
||||
; GCN-NEXT: buffer_load_dword v1, off, s[8:11], 0
|
||||
; GCN-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-NEXT: s_mov_b32 s0, 0xffff
|
||||
; GCN-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-NEXT: s_waitcnt vmcnt(1)
|
||||
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
||||
; GCN-NEXT: v_and_b32_e32 v0, s0, v0
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v1
|
||||
; GCN-NEXT: v_lshl_b32_e32 v0, v1, v0
|
||||
; GCN-NEXT: v_lshl_b32_e32 v1, v2, v3
|
||||
; GCN-NEXT: v_lshl_b32_e32 v0, v2, v0
|
||||
; GCN-NEXT: v_lshl_b32_e32 v1, v1, v3
|
||||
; GCN-NEXT: v_and_b32_e32 v0, s0, v0
|
||||
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; GCN-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
|
|
|
|||
Loading…
Reference in New Issue