forked from OSchip/llvm-project
[X86] Remove some seemingly unnecessary AddedComplexity lines.
Looking at the generated tables this didn't seem to make an obvious difference in pattern priority. llvm-svn: 336555
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@ -711,9 +711,7 @@ multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
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"\t{$src2, $dst|$dst, $src2}">;
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}
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let AddedComplexity = 20 in {
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defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp">;
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}
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defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp">;
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let SchedRW = [WriteFStore] in {
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let Predicates = [UseAVX] in {
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@ -796,9 +794,7 @@ let Predicates = [UseSSE2] in {
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// SSE 1 & 2 - Move Hi packed FP Instructions
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//===----------------------------------------------------------------------===//
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let AddedComplexity = 20 in {
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defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Unpckl, "movhp">;
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}
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defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Unpckl, "movhp">;
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let SchedRW = [WriteFStore] in {
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// v2f64 extract element 1 is always custom lowered to unpack high to low
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@ -889,7 +885,7 @@ let Predicates = [UseSSE2] in {
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// SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
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//===----------------------------------------------------------------------===//
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let AddedComplexity = 20, Predicates = [UseAVX] in {
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let Predicates = [UseAVX] in {
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def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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"movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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@ -904,7 +900,7 @@ let AddedComplexity = 20, Predicates = [UseAVX] in {
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VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG,
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NotMemoryFoldable;
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}
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let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
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let Constraints = "$src1 = $dst" in {
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def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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"movlhps\t{$src2, $dst|$dst, $src2}",
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