forked from OSchip/llvm-project
[mips][ias] Make the default path unreachable in needsRelocateWithSymbol() (except for N64).
Following post-commit comments on r268900 from Rafael Espindola: The missing relocations are now explicitly listed in the switch statement with appropriate FIXME comments and the default path is now unreachable. The temporary exception to this is that compound relocations for N64 still have a default path that returns true. This is because fixing that case ought to be a separate patch. Also make R_MIPS_NONE return false since it has no effect on the section data. llvm-svn: 269047
This commit is contained in:
Daniel Sanders
parent
e243753a4d
commit
2225d9415f
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@ -476,10 +476,21 @@ void MipsELFObjectWriter::sortRelocs(const MCAssembler &Asm,
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bool MipsELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym,
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unsigned Type) const {
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// This must be a compound relocation from the N64 ABI.
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// FIXME: Return false iff all sub-relocations return false.
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if (!isUInt<8>(Type))
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return true;
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switch (Type) {
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default:
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errs() << Type << "\n";
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llvm_unreachable("Unexpected relocation");
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return true;
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// This relocation doesn't affect the section data.
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case ELF::R_MIPS_NONE:
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return false;
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// On REL ABI's (e.g. O32), these relocations form pairs. The pairing is done
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// by the static linker by matching the symbol and offset.
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// We only see one relocation at a time but it's still safe to relocate with
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@ -502,13 +513,115 @@ bool MipsELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym,
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case ELF::R_MIPS_32:
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if (cast<MCSymbolELF>(Sym).getOther() & ELF::STO_MIPS_MICROMIPS)
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return true;
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// falltrough
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// fallthrough
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case ELF::R_MIPS_26:
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case ELF::R_MIPS_64:
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case ELF::R_MIPS_GPREL16:
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case ELF::R_MIPS_GPREL32:
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case ELF::R_MIPS_PC16:
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return false;
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// FIXME: Many of these relocations should probably return false but this
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// hasn't been confirmed to be safe yet.
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case ELF::R_MIPS_REL32:
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case ELF::R_MIPS_LITERAL:
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case ELF::R_MIPS_CALL16:
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case ELF::R_MIPS_SHIFT5:
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case ELF::R_MIPS_SHIFT6:
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case ELF::R_MIPS_GOT_DISP:
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case ELF::R_MIPS_GOT_PAGE:
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case ELF::R_MIPS_GOT_OFST:
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case ELF::R_MIPS_GOT_HI16:
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case ELF::R_MIPS_GOT_LO16:
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case ELF::R_MIPS_SUB:
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case ELF::R_MIPS_INSERT_A:
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case ELF::R_MIPS_INSERT_B:
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case ELF::R_MIPS_DELETE:
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case ELF::R_MIPS_HIGHER:
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case ELF::R_MIPS_HIGHEST:
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case ELF::R_MIPS_CALL_HI16:
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case ELF::R_MIPS_CALL_LO16:
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case ELF::R_MIPS_SCN_DISP:
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case ELF::R_MIPS_REL16:
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case ELF::R_MIPS_ADD_IMMEDIATE:
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case ELF::R_MIPS_PJUMP:
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case ELF::R_MIPS_RELGOT:
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case ELF::R_MIPS_JALR:
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case ELF::R_MIPS_TLS_DTPMOD32:
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case ELF::R_MIPS_TLS_DTPREL32:
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case ELF::R_MIPS_TLS_DTPMOD64:
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case ELF::R_MIPS_TLS_DTPREL64:
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case ELF::R_MIPS_TLS_GD:
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case ELF::R_MIPS_TLS_LDM:
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case ELF::R_MIPS_TLS_DTPREL_HI16:
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case ELF::R_MIPS_TLS_DTPREL_LO16:
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case ELF::R_MIPS_TLS_GOTTPREL:
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case ELF::R_MIPS_TLS_TPREL32:
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case ELF::R_MIPS_TLS_TPREL64:
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case ELF::R_MIPS_TLS_TPREL_HI16:
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case ELF::R_MIPS_TLS_TPREL_LO16:
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case ELF::R_MIPS_GLOB_DAT:
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case ELF::R_MIPS_PC21_S2:
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case ELF::R_MIPS_PC26_S2:
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case ELF::R_MIPS_PC18_S3:
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case ELF::R_MIPS_PC19_S2:
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case ELF::R_MIPS_PCHI16:
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case ELF::R_MIPS_PCLO16:
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case ELF::R_MIPS_COPY:
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case ELF::R_MIPS_JUMP_SLOT:
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case ELF::R_MIPS_NUM:
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case ELF::R_MIPS_PC32:
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case ELF::R_MIPS_EH:
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case ELF::R_MICROMIPS_26_S1:
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case ELF::R_MICROMIPS_GPREL16:
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case ELF::R_MICROMIPS_LITERAL:
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case ELF::R_MICROMIPS_PC7_S1:
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case ELF::R_MICROMIPS_PC10_S1:
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case ELF::R_MICROMIPS_PC16_S1:
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case ELF::R_MICROMIPS_CALL16:
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case ELF::R_MICROMIPS_GOT_DISP:
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case ELF::R_MICROMIPS_GOT_PAGE:
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case ELF::R_MICROMIPS_GOT_OFST:
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case ELF::R_MICROMIPS_GOT_HI16:
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case ELF::R_MICROMIPS_GOT_LO16:
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case ELF::R_MICROMIPS_SUB:
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case ELF::R_MICROMIPS_HIGHER:
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case ELF::R_MICROMIPS_HIGHEST:
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case ELF::R_MICROMIPS_CALL_HI16:
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case ELF::R_MICROMIPS_CALL_LO16:
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case ELF::R_MICROMIPS_SCN_DISP:
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case ELF::R_MICROMIPS_JALR:
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case ELF::R_MICROMIPS_HI0_LO16:
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case ELF::R_MICROMIPS_TLS_GD:
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case ELF::R_MICROMIPS_TLS_LDM:
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case ELF::R_MICROMIPS_TLS_DTPREL_HI16:
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case ELF::R_MICROMIPS_TLS_DTPREL_LO16:
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case ELF::R_MICROMIPS_TLS_GOTTPREL:
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case ELF::R_MICROMIPS_TLS_TPREL_HI16:
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case ELF::R_MICROMIPS_TLS_TPREL_LO16:
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case ELF::R_MICROMIPS_GPREL7_S2:
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case ELF::R_MICROMIPS_PC23_S2:
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case ELF::R_MICROMIPS_PC21_S2:
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case ELF::R_MICROMIPS_PC26_S1:
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case ELF::R_MICROMIPS_PC18_S3:
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case ELF::R_MICROMIPS_PC19_S2:
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return true;
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// FIXME: Many of these should probably return false but MIPS16 isn't
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// supported by the integrated assembler.
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case ELF::R_MIPS16_26:
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case ELF::R_MIPS16_GPREL:
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case ELF::R_MIPS16_CALL16:
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case ELF::R_MIPS16_TLS_GD:
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case ELF::R_MIPS16_TLS_LDM:
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case ELF::R_MIPS16_TLS_DTPREL_HI16:
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case ELF::R_MIPS16_TLS_DTPREL_LO16:
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case ELF::R_MIPS16_TLS_GOTTPREL:
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case ELF::R_MIPS16_TLS_TPREL_HI16:
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case ELF::R_MIPS16_TLS_TPREL_LO16:
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llvm_unreachable("Unsupported MIPS16 relocation");
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return true;
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}
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}
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@ -28,8 +28,8 @@ foo:
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# OBJ-O32: 0000: 00000000 00000000 00000008
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# OBJ-O32-LABEL: }
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# OBJ-O32-LABEL: Relocations [
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# OBJ-O32: 0x0 R_MIPS_NONE foo 0x0
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# OBJ-O32: 0x4 R_MIPS_NONE foo 0x0
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# OBJ-O32: 0x0 R_MIPS_NONE .text 0x0
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# OBJ-O32: 0x4 R_MIPS_NONE .text 0x0
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# OBJ-O32: 0x8 R_MIPS_32 .text 0x0
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# OBJ-O32: 0xC R_MIPS_NONE - 0x0
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@ -43,8 +43,8 @@ foo:
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# OBJ-N32: 0000: 00000000 00000000 00000000
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# OBJ-N32-LABEL: }
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# OBJ-N32-LABEL: Relocations [
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# OBJ-N32: 0x0 R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE foo 0x4
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# OBJ-N32: 0x4 R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE foo 0x0
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# OBJ-N32: 0x0 R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE .text 0x4
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# OBJ-N32: 0x4 R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE .text 0x0
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# OBJ-N32: 0x8 R_MIPS_32/R_MIPS_NONE/R_MIPS_NONE .text 0x8
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# OBJ-N32: 0xC R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE - 0x0
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@ -52,7 +52,7 @@ foo:
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# OBJ-N64: 0000: 00000000 00000000 00000000
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# OBJ-N64-LABEL: }
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# OBJ-N64-LABEL: Relocations [
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# OBJ-N64: 0x0 R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE foo 0x4
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# OBJ-N64: 0x4 R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE foo 0x0
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# OBJ-N64: 0x0 R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE .text 0x4
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# OBJ-N64: 0x4 R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE .text 0x0
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# OBJ-N64: 0x8 R_MIPS_32/R_MIPS_NONE/R_MIPS_NONE .text 0x8
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# OBJ-N64: 0xC R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE - 0x0
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