forked from OSchip/llvm-project
reduce indentation and improve comments, no functionality change.
llvm-svn: 122389
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7089250f5a
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@ -4242,7 +4242,6 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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// of the extended byte. This is not worth optimizing for.
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if (ShAmt >= VT.getSizeInBits())
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return SDValue();
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}
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}
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@ -4250,20 +4249,26 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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// we can fold the truncate through the shift.
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unsigned ShLeftAmt = 0;
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if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
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ExtVT == VT &&
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TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
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ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
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if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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ShLeftAmt = N01->getZExtValue();
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N0 = N0.getOperand(0);
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}
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}
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// If we haven't found a load, we can't narrow it. Don't transform one with
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// multiple uses, this would require adding a new load.
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if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
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// Don't change the width of a volatile load.
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cast<LoadSDNode>(N0)->isVolatile())
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return SDValue();
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// Do not generate loads of non-round integer types since these can
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// be expensive (and would be wrong if the type is not byte sized).
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if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
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cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits &&
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// Do not change the width of a volatile load.
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!cast<LoadSDNode>(N0)->isVolatile()) {
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if (!ExtVT.isRound() ||
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cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
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return SDValue();
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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EVT PtrType = N0.getOperand(1).getValueType();
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@ -4310,9 +4315,6 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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return Result;
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}
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return SDValue();
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}
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SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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