forked from OSchip/llvm-project
[InstCombine/PowerPC] Convert aligned QPX load/store intrinsics into loads/stores
InstCombine has long had logic to convert aligned Altivec load/store intrinsics into regular loads and stores. This mirrors that functionality for QPX vector load/store intrinsics. llvm-svn: 230660
This commit is contained in:
Hal Finkel
parent
093d6e1a70
commit
221f467185
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@ -576,6 +576,44 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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Value *Ptr = Builder->CreateBitCast(II->getArgOperand(1), OpPtrTy);
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return new StoreInst(II->getArgOperand(0), Ptr, false, 1);
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}
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case Intrinsic::ppc_qpx_qvlfs:
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// Turn PPC QPX qvlfs -> load if the pointer is known aligned.
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if (getOrEnforceKnownAlignment(II->getArgOperand(0), 16, DL, AC, II, DT) >=
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16) {
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Value *Ptr = Builder->CreateBitCast(II->getArgOperand(0),
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PointerType::getUnqual(II->getType()));
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return new LoadInst(Ptr);
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}
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break;
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case Intrinsic::ppc_qpx_qvlfd:
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// Turn PPC QPX qvlfd -> load if the pointer is known aligned.
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if (getOrEnforceKnownAlignment(II->getArgOperand(0), 32, DL, AC, II, DT) >=
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32) {
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Value *Ptr = Builder->CreateBitCast(II->getArgOperand(0),
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PointerType::getUnqual(II->getType()));
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return new LoadInst(Ptr);
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}
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break;
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case Intrinsic::ppc_qpx_qvstfs:
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// Turn PPC QPX qvstfs -> store if the pointer is known aligned.
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if (getOrEnforceKnownAlignment(II->getArgOperand(1), 16, DL, AC, II, DT) >=
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16) {
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Type *OpPtrTy =
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PointerType::getUnqual(II->getArgOperand(0)->getType());
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Value *Ptr = Builder->CreateBitCast(II->getArgOperand(1), OpPtrTy);
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return new StoreInst(II->getArgOperand(0), Ptr);
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}
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break;
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case Intrinsic::ppc_qpx_qvstfd:
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// Turn PPC QPX qvstfd -> store if the pointer is known aligned.
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if (getOrEnforceKnownAlignment(II->getArgOperand(1), 32, DL, AC, II, DT) >=
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32) {
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Type *OpPtrTy =
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PointerType::getUnqual(II->getArgOperand(0)->getType());
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Value *Ptr = Builder->CreateBitCast(II->getArgOperand(1), OpPtrTy);
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return new StoreInst(II->getArgOperand(0), Ptr);
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}
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break;
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case Intrinsic::x86_sse_storeu_ps:
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case Intrinsic::x86_sse2_storeu_pd:
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case Intrinsic::x86_sse2_storeu_dq:
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@ -0,0 +1,162 @@
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; RUN: opt -S -instcombine < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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declare <4 x double> @llvm.ppc.qpx.qvlfs(i8*) #1
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define <4 x double> @test1(<4 x float>* %h) #0 {
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entry:
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%h1 = getelementptr <4 x float>* %h, i64 1
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%hv = bitcast <4 x float>* %h1 to i8*
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%vl = call <4 x double> @llvm.ppc.qpx.qvlfs(i8* %hv)
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; CHECK-LABEL: @test1
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; CHECK: @llvm.ppc.qpx.qvlfs
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; CHECK: ret <4 x double>
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%v0 = load <4 x float>* %h, align 8
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%v0e = fpext <4 x float> %v0 to <4 x double>
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%a = fadd <4 x double> %v0e, %vl
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ret <4 x double> %a
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}
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define <4 x double> @test1a(<4 x float>* align 16 %h) #0 {
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entry:
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%h1 = getelementptr <4 x float>* %h, i64 1
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%hv = bitcast <4 x float>* %h1 to i8*
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%vl = call <4 x double> @llvm.ppc.qpx.qvlfs(i8* %hv)
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; CHECK-LABEL: @test1a
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; CHECK-NOT: @llvm.ppc.qpx.qvlfs
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; CHECK: ret <4 x double>
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%v0 = load <4 x float>* %h, align 8
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%v0e = fpext <4 x float> %v0 to <4 x double>
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%a = fadd <4 x double> %v0e, %vl
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ret <4 x double> %a
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}
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declare void @llvm.ppc.qpx.qvstfs(<4 x double>, i8*) #0
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define <4 x float> @test2(<4 x float>* %h, <4 x double> %d) #0 {
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entry:
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%h1 = getelementptr <4 x float>* %h, i64 1
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%hv = bitcast <4 x float>* %h1 to i8*
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call void @llvm.ppc.qpx.qvstfs(<4 x double> %d, i8* %hv)
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%v0 = load <4 x float>* %h, align 8
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ret <4 x float> %v0
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; CHECK-LABEL: @test2
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; CHECK: @llvm.ppc.qpx.qvstfs
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; CHECK: ret <4 x float>
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}
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define <4 x float> @test2a(<4 x float>* align 16 %h, <4 x double> %d) #0 {
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entry:
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%h1 = getelementptr <4 x float>* %h, i64 1
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%hv = bitcast <4 x float>* %h1 to i8*
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call void @llvm.ppc.qpx.qvstfs(<4 x double> %d, i8* %hv)
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%v0 = load <4 x float>* %h, align 8
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ret <4 x float> %v0
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; CHECK-LABEL: @test2
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; CHECK-NOT: @llvm.ppc.qpx.qvstfs
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; CHECK: ret <4 x float>
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}
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declare <4 x double> @llvm.ppc.qpx.qvlfd(i8*) #1
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define <4 x double> @test1l(<4 x double>* %h) #0 {
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entry:
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%h1 = getelementptr <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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%vl = call <4 x double> @llvm.ppc.qpx.qvlfd(i8* %hv)
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; CHECK-LABEL: @test1l
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; CHECK: @llvm.ppc.qpx.qvlfd
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; CHECK: ret <4 x double>
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%v0 = load <4 x double>* %h, align 8
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%a = fadd <4 x double> %v0, %vl
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ret <4 x double> %a
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}
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define <4 x double> @test1ln(<4 x double>* align 16 %h) #0 {
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entry:
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%h1 = getelementptr <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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%vl = call <4 x double> @llvm.ppc.qpx.qvlfd(i8* %hv)
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; CHECK-LABEL: @test1ln
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; CHECK: @llvm.ppc.qpx.qvlfd
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; CHECK: ret <4 x double>
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%v0 = load <4 x double>* %h, align 8
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%a = fadd <4 x double> %v0, %vl
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ret <4 x double> %a
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}
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define <4 x double> @test1la(<4 x double>* align 32 %h) #0 {
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entry:
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%h1 = getelementptr <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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%vl = call <4 x double> @llvm.ppc.qpx.qvlfd(i8* %hv)
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; CHECK-LABEL: @test1la
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; CHECK-NOT: @llvm.ppc.qpx.qvlfd
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; CHECK: ret <4 x double>
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%v0 = load <4 x double>* %h, align 8
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%a = fadd <4 x double> %v0, %vl
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ret <4 x double> %a
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}
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declare void @llvm.ppc.qpx.qvstfd(<4 x double>, i8*) #0
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define <4 x double> @test2l(<4 x double>* %h, <4 x double> %d) #0 {
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entry:
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%h1 = getelementptr <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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call void @llvm.ppc.qpx.qvstfd(<4 x double> %d, i8* %hv)
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%v0 = load <4 x double>* %h, align 8
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ret <4 x double> %v0
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; CHECK-LABEL: @test2l
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; CHECK: @llvm.ppc.qpx.qvstfd
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; CHECK: ret <4 x double>
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}
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define <4 x double> @test2ln(<4 x double>* align 16 %h, <4 x double> %d) #0 {
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entry:
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%h1 = getelementptr <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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call void @llvm.ppc.qpx.qvstfd(<4 x double> %d, i8* %hv)
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%v0 = load <4 x double>* %h, align 8
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ret <4 x double> %v0
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; CHECK-LABEL: @test2ln
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; CHECK: @llvm.ppc.qpx.qvstfd
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; CHECK: ret <4 x double>
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}
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define <4 x double> @test2la(<4 x double>* align 32 %h, <4 x double> %d) #0 {
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entry:
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%h1 = getelementptr <4 x double>* %h, i64 1
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%hv = bitcast <4 x double>* %h1 to i8*
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call void @llvm.ppc.qpx.qvstfd(<4 x double> %d, i8* %hv)
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%v0 = load <4 x double>* %h, align 8
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ret <4 x double> %v0
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; CHECK-LABEL: @test2l
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; CHECK-NOT: @llvm.ppc.qpx.qvstfd
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; CHECK: ret <4 x double>
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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