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[X86] Be explicit about calls to setOperationAction for AVX2 and AVX512 rather than just looping over all vector types and conditinally matching them. NFC 

llvm-svn: 266577
This commit is contained in:
Craig Topper 2016-04-17 22:49:46 +00:00
parent fb9871b495
commit 221e1c2b1f
1 changed files with 41 additions and 44 deletions
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37
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -1159,21 +1159,22 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::SRA, VT, Custom); setOperationAction(ISD::SRA, VT, Custom);
} }
// Custom lower several nodes for 256-bit types. for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
for (MVT VT : MVT::vector_valuetypes()) { MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
if (VT.getScalarSizeInBits() >= 32) {
setOperationAction(ISD::MLOAD, VT, Legal); setOperationAction(ISD::MLOAD, VT, Legal);
setOperationAction(ISD::MSTORE, VT, Legal); setOperationAction(ISD::MSTORE, VT, Legal);
} }
// Extract subvector is special because the value type // Extract subvector is special because the value type
// (result) is 128-bit but the source is 256-bit wide. // (result) is 128-bit but the source is 256-bit wide.
if (VT.is128BitVector()) { for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
MVT::v4f32, MVT::v2f64 }) {
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
} }
// Do not attempt to custom lower other non-256-bit vectors
if (!VT.is256BitVector())
continue;
// Custom lower several nodes for 256-bit types.
for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
MVT::v8f32, MVT::v4f64 }) {
setOperationAction(ISD::BUILD_VECTOR, VT, Custom); setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::VSELECT, VT, Custom); setOperationAction(ISD::VSELECT, VT, Custom);
@ -1446,25 +1447,22 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::MUL, MVT::v8i64, Legal); setOperationAction(ISD::MUL, MVT::v8i64, Legal);
} }
// Custom lower several nodes. // Custom lower several nodes.
for (MVT VT : MVT::vector_valuetypes()) { for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
unsigned EltSize = VT.getVectorElementType().getSizeInBits(); MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
if ((VT.is128BitVector() || VT.is256BitVector()) && EltSize >= 32) {
setOperationAction(ISD::MGATHER, VT, Custom); setOperationAction(ISD::MGATHER, VT, Custom);
setOperationAction(ISD::MSCATTER, VT, Custom); setOperationAction(ISD::MSCATTER, VT, Custom);
} }
// Extract subvector is special because the value type // Extract subvector is special because the value type
// (result) is 256/128-bit but the source is 512-bit wide. // (result) is 256-bit but the source is 512-bit wide.
if (VT.is128BitVector() || VT.is256BitVector()) { // 128-bit was made Custom under AVX1.
for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
MVT::v8f32, MVT::v4f64 })
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
} for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1,
if (VT.getVectorElementType() == MVT::i1) MVT::v16i1, MVT::v32i1, MVT::v64i1 })
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
// Do not attempt to custom lower other non-512-bit vectors for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
if (!VT.is512BitVector())
continue;
if (EltSize >= 32) {
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom); setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
@ -1477,7 +1475,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::MGATHER, VT, Legal); setOperationAction(ISD::MGATHER, VT, Legal);
setOperationAction(ISD::MSCATTER, VT, Custom); setOperationAction(ISD::MSCATTER, VT, Custom);
} }
}
for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) { for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
setOperationPromotedToType(ISD::SELECT, VT, MVT::v8i64); setOperationPromotedToType(ISD::SELECT, VT, MVT::v8i64);
} }